| /art/disassembler/ |
| D | disassembler_arm.cc | 252 std::string opcode; in DumpArm() local
260 opcode = "bkpt"; in DumpArm()
267 opcode = (((instruction >> 5) & 1) ? "blx" : "bx"); in DumpArm()
274 opcode = kDataProcessingOperations[op]; in DumpArm()
313 opcode = StringPrintf("%s%s", (l ? "ldr" : "str"), (b ? "b" : "")); in DumpArm()
343 opcode = StringPrintf("%s%c%c", (l ? "ldm" : "stm"), (u ? 'i' : 'd'), (p ? 'b' : 'a')); in DumpArm()
350 opcode = (bl ? "bl" : "b"); in DumpArm()
357 opcode = "???"; in DumpArm()
360 opcode += kConditionCodeNames[cond]; in DumpArm()
361 opcode += suffixes; in DumpArm()
[all …]
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| /art/tools/dexfuzz/src/dexfuzz/program/mutators/ |
| D | ValuePrinter.java | 216 Opcode opcode = mInsn.insn.info.opcode; in getInstructionOutputType() local
217 if (opcode == Opcode.CONST_STRING || opcode == Opcode.CONST_STRING_JUMBO) { in getInstructionOutputType()
220 if (opcode == Opcode.IGET_BOOLEAN || opcode == Opcode.SGET_BOOLEAN) { in getInstructionOutputType()
223 if (opcode == Opcode.IGET_BYTE || opcode == Opcode.SGET_BYTE in getInstructionOutputType()
224 || opcode == Opcode.INT_TO_BYTE) { in getInstructionOutputType()
227 if (opcode == Opcode.IGET_CHAR || opcode == Opcode.SGET_CHAR in getInstructionOutputType()
228 || opcode == Opcode.INT_TO_CHAR) { in getInstructionOutputType()
231 if (opcode == Opcode.IGET_SHORT || opcode == Opcode.SGET_SHORT in getInstructionOutputType()
232 || opcode == Opcode.INT_TO_SHORT) { in getInstructionOutputType()
235 if (opcode == Opcode.NEG_INT || opcode == Opcode.NOT_INT in getInstructionOutputType()
[all …]
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| /art/runtime/ |
| D | dex_instruction_utils.h | 54 constexpr bool IsInstructionDirectConst(Instruction::Code opcode) { in IsInstructionDirectConst() argument
55 return Instruction::CONST_4 <= opcode && opcode <= Instruction::CONST_WIDE_HIGH16; in IsInstructionDirectConst()
58 constexpr bool IsInstructionConstWide(Instruction::Code opcode) { in IsInstructionConstWide() argument
59 return Instruction::CONST_WIDE_16 <= opcode && opcode <= Instruction::CONST_WIDE_HIGH16; in IsInstructionConstWide()
62 constexpr bool IsInstructionReturn(Instruction::Code opcode) { in IsInstructionReturn() argument
63 return Instruction::RETURN_VOID <= opcode && opcode <= Instruction::RETURN_OBJECT; in IsInstructionReturn()
66 constexpr bool IsInstructionInvoke(Instruction::Code opcode) { in IsInstructionInvoke() argument
67 return Instruction::INVOKE_VIRTUAL <= opcode && opcode <= Instruction::INVOKE_INTERFACE_RANGE && in IsInstructionInvoke()
68 opcode != Instruction::RETURN_VOID_NO_BARRIER; in IsInstructionInvoke()
71 constexpr bool IsInstructionQuickInvoke(Instruction::Code opcode) { in IsInstructionQuickInvoke() argument
[all …]
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| D | dex_instruction.cc | 71 #define INSTRUCTION_SIZE(opcode, c, p, format, r, i, a, v) \ argument
72 ((opcode == NOP) ? -1 : \
101 Code opcode = static_cast<Code>(insn & 0xFF); in CanFlowThrough() local
102 return FlagsOf(opcode) & Instruction::kContinue; in CanFlowThrough()
164 const char* opcode = kInstructionNames[Opcode()]; in DumpString() local
166 case k10x: os << opcode; break; in DumpString()
167 case k12x: os << StringPrintf("%s v%d, v%d", opcode, VRegA_12x(), VRegB_12x()); break; in DumpString()
168 case k11n: os << StringPrintf("%s v%d, #%+d", opcode, VRegA_11n(), VRegB_11n()); break; in DumpString()
169 case k11x: os << StringPrintf("%s v%d", opcode, VRegA_11x()); break; in DumpString()
170 case k10t: os << StringPrintf("%s %+d", opcode, VRegA_10t()); break; in DumpString()
[all …]
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| /art/runtime/interpreter/mterp/x86/ |
| D | op_cmp_long.S | 10 jl .L${opcode}_smaller
11 jg .L${opcode}_bigger
15 ja .L${opcode}_bigger
16 jb .L${opcode}_smaller
17 .L${opcode}_finish:
21 .L${opcode}_bigger:
23 jmp .L${opcode}_finish
25 .L${opcode}_smaller:
27 jmp .L${opcode}_finish
|
| D | fpcmp.S | 24 jp .L${opcode}_nan_is_${nanval}
25 je .L${opcode}_finish
26 jb .L${opcode}_less
27 .L${opcode}_nan_is_pos:
29 jmp .L${opcode}_finish
30 .L${opcode}_nan_is_neg:
31 .L${opcode}_less:
33 .L${opcode}_finish:
|
| D | bindiv.S | 18 jz .L${opcode}_8 # Do 8-bit divide
21 jz .L${opcode}_16 # Do 16-bit divide
23 jne .L${opcode}_32
25 jne .L${opcode}_32
27 jmp .L${opcode}_finish
28 .L${opcode}_32:
31 jmp .L${opcode}_finish
32 .L${opcode}_8:
41 jmp .L${opcode}_finish
42 .L${opcode}_16:
[all …]
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| D | cvtfp_int.S | 37 je .L${opcode}_special_case # fix up result
39 .L${opcode}_finish:
47 .L${opcode}_special_case:
50 jp .L${opcode}_isNaN
55 jmp .L${opcode}_finish
56 .L${opcode}_isNaN:
61 jmp .L${opcode}_finish
|
| /art/runtime/interpreter/mterp/x86_64/ |
| D | fpcmp.S | 24 jp .L${opcode}_nan_is_${nanval}
25 je .L${opcode}_finish
26 jb .L${opcode}_less
27 .L${opcode}_nan_is_pos:
29 jmp .L${opcode}_finish
30 .L${opcode}_nan_is_neg:
31 .L${opcode}_less:
33 .L${opcode}_finish:
|
| /art/runtime/interpreter/mterp/mips/ |
| D | op_cmpl_float.S | 32 bc1nez ft2, .L${opcode}_finish
35 bc1nez ft2, .L${opcode}_finish
38 bc1nez ft2, .L${opcode}_finish
39 b .L${opcode}_nan
43 bc1t fcc0, .L${opcode}_finish
46 bc1t fcc0, .L${opcode}_finish
49 bc1t fcc0, .L${opcode}_finish
50 b .L${opcode}_nan
54 .L${opcode}_nan:
57 .L${opcode}_finish:
[all …]
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| D | op_cmpl_double.S | 25 bc1nez ft2, .L${opcode}_finish
28 bc1nez ft2, .L${opcode}_finish
31 bc1nez ft2, .L${opcode}_finish
32 b .L${opcode}_nan
36 bc1t fcc0, .L${opcode}_finish
39 bc1t fcc0, .L${opcode}_finish
42 bc1t fcc0, .L${opcode}_finish
43 b .L${opcode}_nan
47 .L${opcode}_nan:
50 .L${opcode}_finish:
[all …]
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| D | op_float_to_long.S | 10 bc1nez ft2, .L${opcode}_set_vreg
16 bc1nez ft2, .L${opcode}_set_vreg
22 bc1nez ft2, .L${opcode}_set_vreg
28 bc1t .L${opcode}_set_vreg
34 bc1t .L${opcode}_set_vreg
40 bc1t .L${opcode}_set_vreg
45 b .L${opcode}_set_vreg
|
| D | op_float_to_int.S | 12 bc1nez ft2, .L${opcode}_set_vreg_f
17 bc1nez ft2, .L${opcode}_set_vreg_f
22 bc1nez ft2, .L${opcode}_set_vreg_f
27 bc1t .L${opcode}_set_vreg_f
32 bc1t .L${opcode}_set_vreg_f
37 bc1t .L${opcode}_set_vreg_f
41 b .L${opcode}_set_vreg_f
|
| D | op_double_to_int.S | 17 bc1nez ft2, .L${opcode}_set_vreg_f
23 bc1nez ft2, .L${opcode}_set_vreg_f
28 bc1nez ft2, .L${opcode}_set_vreg_f
34 bc1t .L${opcode}_set_vreg_f
40 bc1t .L${opcode}_set_vreg_f
45 bc1t .L${opcode}_set_vreg_f
49 b .L${opcode}_set_vreg_f
|
| D | op_double_to_long.S | 11 bc1nez ft2, .L${opcode}_set_vreg
18 bc1nez ft2, .L${opcode}_set_vreg
24 bc1nez ft2, .L${opcode}_set_vreg
31 bc1t .L${opcode}_set_vreg
38 bc1t .L${opcode}_set_vreg
44 bc1t .L${opcode}_set_vreg
47 b .L${opcode}_set_vreg
|
| /art/tools/dexfuzz/src/dexfuzz/rawdex/ |
| D | CodeItem.java | 149 Opcode opcode = insn.info.opcode; in incrementIndex() local
152 if (opcode == Opcode.CONST_STRING || opcode == Opcode.CONST_STRING_JUMBO) { in incrementIndex()
160 if (opcode == Opcode.CONST_CLASS in incrementIndex()
161 || opcode == Opcode.CHECK_CAST in incrementIndex()
162 || opcode == Opcode.NEW_INSTANCE in incrementIndex()
163 || opcode == Opcode.FILLED_NEW_ARRAY in incrementIndex()
164 || opcode == Opcode.FILLED_NEW_ARRAY_RANGE) { in incrementIndex()
169 } else if (opcode == Opcode.INSTANCE_OF || opcode == Opcode.NEW_ARRAY) { in incrementIndex()
177 if (Opcode.isBetween(opcode, Opcode.SGET, Opcode.SPUT_SHORT)) { in incrementIndex()
182 } else if (Opcode.isBetween(opcode, Opcode.IGET, Opcode.IPUT_SHORT)) { in incrementIndex()
[all …]
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| D | OpcodeInfo.java | 27 public final Opcode opcode; field in OpcodeInfo
35 public OpcodeInfo(Opcode opcode, String name, int opcodeValue, AbstractFormat fmt) { in OpcodeInfo() argument
36 this.opcode = opcode; in OpcodeInfo()
|
| /art/runtime/interpreter/mterp/mips64/ |
| D | op_double_to_int.S | 9 bc1nez f1, .L${opcode}_trunc
14 b .L${opcode}_done
16 .L${opcode}_trunc:
19 .L${opcode}_done:
21 GET_INST_OPCODE v0 # extract opcode from rINST
|
| D | op_double_to_long.S | 9 bc1nez f1, .L${opcode}_trunc
14 b .L${opcode}_done
16 .L${opcode}_trunc:
19 .L${opcode}_done:
21 GET_INST_OPCODE v0 # extract opcode from rINST
|
| D | op_float_to_int.S | 9 bc1nez f1, .L${opcode}_trunc
14 b .L${opcode}_done
16 .L${opcode}_trunc:
19 .L${opcode}_done:
21 GET_INST_OPCODE v0 # extract opcode from rINST
|
| D | op_float_to_long.S | 9 bc1nez f1, .L${opcode}_trunc
14 b .L${opcode}_done
16 .L${opcode}_trunc:
19 .L${opcode}_done:
21 GET_INST_OPCODE v0 # extract opcode from rINST
|
| /art/runtime/interpreter/mterp/arm64/ |
| D | op_return_void_no_barrier.S | 4 b.ne .L${opcode}_check
5 .L${opcode}_return:
8 .L${opcode}_check:
10 b .L${opcode}_return
|
| D | op_return_void.S | 6 b.ne .L${opcode}_check
7 .L${opcode}_return:
10 .L${opcode}_check:
12 b .L${opcode}_return
|
| D | op_return_wide.S | 11 b.ne .L${opcode}_check
12 .L${opcode}_return:
16 .L${opcode}_check:
18 b .L${opcode}_return
|
| D | op_return.S | 12 b.ne .L${opcode}_check
13 .L${opcode}_return:
17 .L${opcode}_check:
19 b .L${opcode}_return
|