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Searched refs:AM (Results 1 – 25 of 531) sorted by relevance

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/external/llvm/lib/Target/MSP430/
DMSP430ISelDAGToDAG.cpp103 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
104 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
105 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
135 bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) { in MatchWrapper() argument
138 if (AM.hasSymbolicDisplacement()) in MatchWrapper()
144 AM.GV = G->getGlobal(); in MatchWrapper()
145 AM.Disp += G->getOffset(); in MatchWrapper()
148 AM.CP = CP->getConstVal(); in MatchWrapper()
149 AM.Align = CP->getAlignment(); in MatchWrapper()
150 AM.Disp += CP->getOffset(); in MatchWrapper()
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/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp203 bool foldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
204 bool matchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
205 bool matchWrapper(SDValue N, X86ISelAddressMode &AM);
206 bool matchAddress(SDValue N, X86ISelAddressMode &AM);
207 bool matchAdd(SDValue N, X86ISelAddressMode &AM, unsigned Depth);
208 bool matchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
210 bool matchAddressBase(SDValue N, X86ISelAddressMode &AM);
245 inline void getAddressOperands(X86ISelAddressMode &AM, SDLoc DL, in getAddressOperands() argument
249 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) in getAddressOperands()
251 AM.Base_FrameIndex, in getAddressOperands()
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DX86InstrBuilder.h124 const X86AddressMode &AM) { in addFullAddress() argument
125 assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8); in addFullAddress()
127 if (AM.BaseType == X86AddressMode::RegBase) in addFullAddress()
128 MIB.addReg(AM.Base.Reg); in addFullAddress()
130 assert(AM.BaseType == X86AddressMode::FrameIndexBase); in addFullAddress()
131 MIB.addFrameIndex(AM.Base.FrameIndex); in addFullAddress()
134 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
135 if (AM.GV) in addFullAddress()
136 MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags); in addFullAddress()
138 MIB.addImm(AM.Disp); in addFullAddress()
DX86FastISel.cpp87 bool X86FastEmitLoad(EVT VT, X86AddressMode &AM, MachineMemOperand *MMO,
90 bool X86FastEmitStore(EVT VT, const Value *Val, X86AddressMode &AM,
93 X86AddressMode &AM,
99 bool X86SelectAddress(const Value *V, X86AddressMode &AM);
100 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM);
142 bool handleConstantAddresses(const Value *V, X86AddressMode &AM);
171 X86AddressMode &AM);
255 X86AddressMode &AM) { in addFullAddress() argument
257 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
260 return ::addFullAddress(MIB, AM); in addFullAddress()
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/external/curl/tests/data/
Dtest111442 Time: 04-27-10 05:12AM
48 Time: 04-23-10 03:12AM
54 Time: 01-11-10 10:00AM
64 Time: 02-01-10 08:00AM
74 Time: 02-01-10 08:00AM
84 Time: 05-04-10 04:31AM
90 Time: 05-04-10 04:31AM
96 Time: 04-27-10 11:01AM
105 Time: 04-27-10 11:01AM
115 Time: 01-23-05 02:05AM
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/external/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp150 bool expandAddress(SystemZAddressingMode &AM, bool IsBase) const;
153 bool selectAddress(SDValue N, SystemZAddressingMode &AM) const;
156 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
158 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
381 static void changeComponent(SystemZAddressingMode &AM, bool IsBase, in changeComponent() argument
384 AM.Base = Value; in changeComponent()
386 AM.Index = Value; in changeComponent()
392 static bool expandAdjDynAlloc(SystemZAddressingMode &AM, bool IsBase, in expandAdjDynAlloc() argument
394 if (AM.isDynAlloc() && !AM.IncludesDynAlloc) { in expandAdjDynAlloc()
395 changeComponent(AM, IsBase, Value); in expandAdjDynAlloc()
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/external/v8/test/webkit/
Ddate-parse-comments-test-expected.txt53 PASS Date.parse("(Nov) Dec (24) 25 (26) 1995 (1996) 1:30 AM (1:40 PM) GMT (EST)") == 819855000000 i…
54 PASS Date.parse("(NOV) DEC (24) 25 (26) 1995 (1996) 1:30 AM (1:40 PM) GMT (EST)") == 819855000000 i…
56 PASS Date.parse("(Nov) Dec (24) 25 (26) 1995 (1996) 1:30 AM (1:40 PM)") == 819855000000 + timeZoneO…
57 PASS Date.parse("(NOV) DEC (24) 25 (26) 1995 (1996) 1:30 AM (1:40 PM)") == 819855000000 + timeZoneO…
59 PASS Date.parse("Dec 25 1995 1:30( )AM (PM)") is NaN
60 PASS Date.parse("DEC 25 1995 1:30( )AM (PM)") is NaN
62 PASS Date.parse("Dec 25 1995 1:30 AM (PM)") == 819855000000 + timeZoneOffset is true
63 PASS Date.parse("DEC 25 1995 1:30 AM (PM)") == 819855000000 + timeZoneOffset is true
77 PASS Date.parse("(Nov) Dec (24) 25 (26) 1995 (1996) 1:30 (1:40) PM (AM) GMT (PST)") == 819898200000…
78 PASS Date.parse("(NOV) DEC (24) 25 (26) 1995 (1996) 1:30 (1:40) PM (AM) GMT (PST)") == 819898200000…
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/external/llvm/unittests/IR/
DPassManagerTest.cpp38 Result run(Function &F, FunctionAnalysisManager *AM) { in run() argument
70 Result run(Module &M, ModuleAnalysisManager *AM) { in run() argument
106 PreservedAnalyses run(Module &M, ModuleAnalysisManager *AM) { in run()
110 (void)AM->getResult<TestModuleAnalysis>(M); in run()
127 PreservedAnalyses run(Function &F, FunctionAnalysisManager *AM) { in run()
131 AM->getResult<ModuleAnalysisManagerFunctionProxy>(F).getManager(); in run()
139 AM->getCachedResult<TestFunctionAnalysis>(F)) in run()
143 TestFunctionAnalysis::Result &AR = AM->getResult<TestFunctionAnalysis>(F); in run()
/external/llvm/include/llvm/IR/
DPassManager.h198 PreservedAnalyses run(IRUnitT &IR, AnalysisManager<IRUnitT> *AM = nullptr) {
209 PreservedAnalyses PassPA = Passes[Idx]->run(IR, AM);
216 if (AM)
217 PassPA = AM->invalidate(IR, std::move(PassPA));
786 PreservedAnalyses run(Module &M, ModuleAnalysisManager *AM) { in run() argument
788 if (AM) in run()
790 FAM = &AM->getResult<FunctionAnalysisManagerModuleProxy>(M).getManager(); in run()
846 PreservedAnalyses run(IRUnitT &Arg, AnalysisManager<IRUnitT> *AM) { in run()
847 if (AM) in run()
848 (void)AM->template getResult<AnalysisT>(Arg); in run()
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DPassManagerInternal.h43 virtual PreservedAnalyses run(IRUnitT &IR, AnalysisManager<IRUnitT> *AM) = 0;
99 PreservedAnalysesT run(IRUnitT &IR, AnalysisManager<IRUnitT> *AM) override {
100 return Pass.run(IR, AM);
125 PreservedAnalysesT run(IRUnitT &IR, AnalysisManager<IRUnitT> *AM) override {
255 run(IRUnitT &IR, AnalysisManager<IRUnitT> *AM) = 0;
297 run(IRUnitT &IR, AnalysisManager<IRUnitT> *AM) override {
298 return make_unique<ResultModelT>(Pass.run(IR, AM));
/external/llvm/include/llvm/Analysis/
DCGSCCPassManager.h218 PreservedAnalyses run(Module &M, ModuleAnalysisManager *AM) { in run() argument
219 assert(AM && "We need analyses to compute the call graph!"); in run()
223 AM->getResult<CGSCCAnalysisManagerModuleProxy>(M).getManager(); in run()
226 LazyCallGraph &CG = AM->getResult<LazyCallGraphAnalysis>(M); in run()
442 PreservedAnalyses run(LazyCallGraph::SCC &C, CGSCCAnalysisManager *AM) { in run() argument
444 if (AM) in run()
446 FAM = &AM->getResult<FunctionAnalysisManagerCGSCCProxy>(C).getManager(); in run()
/external/llvm/include/llvm/CodeGen/
DBasicTTIImpl.h124 TargetLoweringBase::AddrMode AM; in isLegalAddressingMode() local
125 AM.BaseGV = BaseGV; in isLegalAddressingMode()
126 AM.BaseOffs = BaseOffset; in isLegalAddressingMode()
127 AM.HasBaseReg = HasBaseReg; in isLegalAddressingMode()
128 AM.Scale = Scale; in isLegalAddressingMode()
129 return getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace); in isLegalAddressingMode()
134 TargetLoweringBase::AddrMode AM; in getScalingFactorCost() local
135 AM.BaseGV = BaseGV; in getScalingFactorCost()
136 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
137 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
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/external/llvm/lib/Analysis/
DScalarEvolutionAliasAnalysis.cpp114 SCEVAAResult SCEVAA::run(Function &F, AnalysisManager<Function> *AM) { in run() argument
115 return SCEVAAResult(AM->getResult<TargetLibraryAnalysis>(F), in run()
116 AM->getResult<ScalarEvolutionAnalysis>(F)); in run()
DTypeBasedAliasAnalysis.cpp289 const MDNode *AM = LocA.AATags.TBAA; in alias() local
290 if (!AM) in alias()
297 if (Aliases(AM, BM)) in alias()
587 TypeBasedAAResult TypeBasedAA::run(Function &F, AnalysisManager<Function> *AM) { in run() argument
588 return TypeBasedAAResult(AM->getResult<TargetLibraryAnalysis>(F)); in run()
DAssumptionCache.cpp80 AnalysisManager<Function> *AM) { in run() argument
81 AssumptionCache &AC = AM->getResult<AssumptionAnalysis>(F); in run()
DObjCARCAliasAnalysis.cpp134 ObjCARCAAResult ObjCARCAA::run(Function &F, AnalysisManager<Function> *AM) { in run() argument
136 AM->getResult<TargetLibraryAnalysis>(F)); in run()
DScopedNoAliasAA.cpp177 AnalysisManager<Function> *AM) { in run() argument
178 return ScopedNoAliasAAResult(AM->getResult<TargetLibraryAnalysis>(F)); in run()
/external/llvm/lib/IR/
DDominators.cpp316 FunctionAnalysisManager *AM) { in run() argument
318 AM->getResult<DominatorTreeAnalysis>(F).print(OS); in run()
324 FunctionAnalysisManager *AM) { in run() argument
325 AM->getResult<DominatorTreeAnalysis>(F).verifyDomTree(); in run()
/external/llvm/lib/Transforms/Scalar/
DSimplifyCFGPass.cpp181 AnalysisManager<Function> *AM) { in run() argument
182 auto &TTI = AM->getResult<TargetIRAnalysis>(F); in run()
183 auto &AC = AM->getResult<AssumptionAnalysis>(F); in run()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp361 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { in getIndexedModeName() argument
362 switch (AM) { in getIndexedModeName()
508 const char *AM = getIndexedModeName(LD->getAddressingMode()); in print_details() local
509 if (*AM) in print_details()
510 OS << ", " << AM; in print_details()
519 const char *AM = getIndexedModeName(ST->getAddressingMode()); in print_details() local
520 if (*AM) in print_details()
521 OS << ", " << AM; in print_details()
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.h62 bool isLegalFlatAddressingMode(const AddrMode &AM) const;
63 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
70 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
DSIISelLowering.cpp302 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const { in isLegalFlatAddressingMode()
305 return AM.BaseOffs == 0 && (AM.Scale == 0 || AM.Scale == 1); in isLegalFlatAddressingMode()
308 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const { in isLegalMUBUFAddressingMode()
318 if (!isUInt<12>(AM.BaseOffs)) in isLegalMUBUFAddressingMode()
324 switch (AM.Scale) { in isLegalMUBUFAddressingMode()
330 if (AM.HasBaseReg) { in isLegalMUBUFAddressingMode()
344 const AddrMode &AM, Type *Ty, in isLegalAddressingMode() argument
347 if (AM.BaseGV) in isLegalAddressingMode()
362 return isLegalFlatAddressingMode(AM); in isLegalAddressingMode()
365 return isLegalMUBUFAddressingMode(AM); in isLegalAddressingMode()
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.h316 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
324 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
534 ISD::MemIndexedMode &AM, bool &IsInc,
537 ISD::MemIndexedMode &AM,
540 SDValue &Offset, ISD::MemIndexedMode &AM,
/external/llvm/include/llvm/Transforms/Scalar/
DEarlyCSE.h34 PreservedAnalyses run(Function &F, AnalysisManager<Function> *AM);
DSimplifyCFG.h41 PreservedAnalyses run(Function &F, AnalysisManager<Function> *AM);

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