| /external/vixl/src/vixl/a64/ |
| D | decoder-a64.cc | 163 VIXL_ASSERT(instr->Bit(28) == 0x1); in DecodePCRelAddressing()
182 if (instr->Bit(25) == 0) { in DecodeBranchSystemException()
190 if (instr->Bit(25) == 0) { in DecodeBranchSystemException()
191 if ((instr->Bit(24) == 0x1) || in DecodeBranchSystemException()
203 if (instr->Bit(25) == 0) { in DecodeBranchSystemException()
204 if (instr->Bit(24) == 0) { in DecodeBranchSystemException()
247 if ((instr->Bit(24) == 0x1) || in DecodeBranchSystemException()
275 if ((instr->Bit(28) == 0) && (instr->Bit(29) == 0) && (instr->Bit(26) == 1)) { in DecodeLoadStore()
280 if (instr->Bit(24) == 0) { in DecodeLoadStore()
281 if (instr->Bit(28) == 0) { in DecodeLoadStore()
[all …]
|
| D | macro-assembler-a64.cc | 2445 IncludeByRegList(available_, list.list() & ~(xzr.Bit() | sp.Bit())); in Include()
2458 RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); in Include()
2460 include &= ~(xzr.Bit() | sp.Bit()); in Include()
2470 RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); in Include()
2489 RegList exclude = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); in Exclude()
2498 RegList excludefp = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); in Exclude()
2514 exclude |= regs[i].Bit(); in Exclude()
2516 excludefp |= regs[i].Bit(); in Exclude()
|
| /external/v8/src/arm64/ |
| D | decoder-arm64-inl.h | 102 DCHECK(instr->Bit(28) == 0x1); in DecodePCRelAddressing()
122 if (instr->Bit(25) == 0) { in DecodeBranchSystemException()
130 if (instr->Bit(25) == 0) { in DecodeBranchSystemException()
131 if ((instr->Bit(24) == 0x1) || in DecodeBranchSystemException()
143 if (instr->Bit(25) == 0) { in DecodeBranchSystemException()
144 if (instr->Bit(24) == 0) { in DecodeBranchSystemException()
187 if ((instr->Bit(24) == 0x1) || in DecodeBranchSystemException()
216 if (instr->Bit(24) == 0) { in DecodeLoadStore()
217 if (instr->Bit(28) == 0) { in DecodeLoadStore()
218 if (instr->Bit(29) == 0) { in DecodeLoadStore()
[all …]
|
| D | assembler-arm64.h | 96 RegList Bit() const;
386 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
476 if (!other1.IsNone() && (other1.type() == type_)) list |= other1.Bit();
477 if (!other2.IsNone() && (other2.type() == type_)) list |= other2.Bit();
478 if (!other3.IsNone() && (other3.type() == type_)) list |= other3.Bit();
479 if (!other4.IsNone() && (other4.type() == type_)) list |= other4.Bit();
|
| /external/v8/src/arm/ |
| D | constants-arm.h | 481 inline int Bit(int nr) const { in Bit() function
498 static inline int Bit(Instr instr, int nr) { in Bit() function
551 inline int NValue() const { return Bit(7); } in NValue()
552 inline int MValue() const { return Bit(5); } in MValue()
553 inline int DValue() const { return Bit(22); } in DValue()
555 inline int PValue() const { return Bit(24); } in PValue()
556 inline int UValue() const { return Bit(23); } in UValue()
557 inline int Opc1Value() const { return (Bit(23) << 2) | Bits(21, 20); } in Opc1Value()
560 inline int SzValue() const { return Bit(8); } in SzValue()
561 inline int VLValue() const { return Bit(20); } in VLValue()
[all …]
|
| D | disasm-arm.cc | 240 shift_names[instr->Bit(6) * 2], in PrintShiftSat()
364 (instr->Bit(24) == 0x0) && in FormatVFPRegister()
366 (instr->Bit(4) == 0x1)) { in FormatVFPRegister()
368 reg = instr->Bits(19, 16) | (instr->Bit(7) << 4); in FormatVFPRegister()
451 if (instr->Bit(21) == 0) { in FormatOption()
477 if (instr->Bit(21) == 0) { in FormatOption()
527 if ((instr->Bits(27, 25) == 0) && (instr->Bit(20) == 0) && in FormatOption()
528 (instr->Bits(7, 6) == 3) && (instr->Bit(4) == 1)) { in FormatOption()
529 if (instr->Bit(5) == 1) { in FormatOption()
621 if (instr->Bit(22) == 0) { in FormatOption()
[all …]
|
| D | constants-arm.cc | 23 high16 |= (0xff * Bit(18)) << 6; // xxbbbbbb,bbxxxxxx. in DoubleImmedVmov()
24 high16 |= (Bit(18) ^ 1) << 14; // xBxxxxxx,xxxxxxxx. in DoubleImmedVmov()
25 high16 |= Bit(19) << 15; // axxxxxxx,xxxxxxxx. in DoubleImmedVmov()
|
| D | simulator-arm.cc | 1428 if (instr->Bit(4) == 0) { in GetShiftRm()
2125 if (instr->Bit(24) == 0) { in DecodeType01()
2133 if (instr->Bit(23) == 0) { in DecodeType01()
2134 if (instr->Bit(21) == 0) { in DecodeType01()
2148 if (instr->Bit(22) == 0) { in DecodeType01()
2179 if (instr->Bit(22) == 1) { in DecodeType01()
2208 if (instr->Bit(22) == 0) { in DecodeType01()
2296 if (((instr->Bits(7, 4) & 0xd) == 0xd) && (instr->Bit(20) == 0)) { in DecodeType01()
2708 if (instr->Bit(4) == 0) { in DecodeType3()
2711 if (instr->Bit(5) == 0) { in DecodeType3()
[all …]
|
| /external/v8/src/ppc/ |
| D | simulator-ppc.cc | 1667 if (instr->Bit(0) == 1) { // LK flag set in ExecuteBranchConditional()
1740 if (instr->Bit(0)) { // RC bit set in ExecuteExt2_10bit()
1754 if (instr->Bit(0)) { // RC bit set in ExecuteExt2_10bit()
1768 if (instr->Bit(0)) { // RC bit set in ExecuteExt2_10bit()
1782 if (instr->Bit(0)) { // RC bit set in ExecuteExt2_10bit()
1795 if (instr->Bit(0)) { // RC bit set in ExecuteExt2_10bit()
1808 if (instr->Bit(0)) { // RC bit set in ExecuteExt2_10bit()
1821 if (instr->Bit(0)) { // RC bit set in ExecuteExt2_10bit()
1833 if (instr->Bit(0)) { // RC bit set in ExecuteExt2_10bit()
1952 int sh = (instr->Bits(15, 11) | (instr->Bit(1) << 5)); in ExecuteExt2_10bit()
[all …]
|
| D | disasm-ppc.cc | 205 if (instr->Bit(10) == 1) { in FormatOption()
211 if (instr->Bit(0) == 1) { in FormatOption()
236 if (instr->Bit(0) == 1) { in FormatOption()
243 if (instr->Bit(1) == 1) { in FormatOption()
280 value = (sh | (instr->Bit(1) << 5)); in FormatOption()
296 value = (instr->Bits(10, 6) | (instr->Bit(5) << 5)); in FormatOption()
304 value = (instr->Bits(10, 6) | (instr->Bit(5) << 5)); in FormatOption()
483 if (instr->Bit(0) == 1) { in DecodeExt1()
637 if (instr->Bit(21)) { in DecodeExt2()
693 if (instr->Bit(21)) { in DecodeExt2()
[all …]
|
| D | constants-ppc.h | 515 inline int Bit(int nr) const { return (InstructionBits() >> nr) & 1; } in Bit() function
530 static inline int Bit(Instr instr, int nr) { return (instr >> nr) & 1; } in Bit() function
|
| /external/vulkan-validation-layers/libs/glm/detail/ |
| D | func_integer.inl | 361 for(int Bit = Offset; Bit < Offset + Bits; ++Bit) local
362 Mask |= (1 << Bit);
490 genIUType Bit; local
491 for(Bit = genIUType(0); !(Value & (1 << Bit)); ++Bit){}
492 return Bit;
577 __m128i Bit = _mm_set_epi32(-1, -1, -1, -1);
584 Bit = _mm_add_epi32(Bit, _mm_and_si128(Shilt, i));
587 return Bit;
603 genIUType Bit = genIUType(-1); local
604 for(genIUType tmp = Value; tmp > 0; tmp >>= 1, ++Bit){}
[all …]
|
| /external/clang/test/Parser/ |
| D | MicrosoftExtensionsInlineAsm.c | 5 void __forceinline InterlockedBitTestAndSet (long *Base, long Bit) in InterlockedBitTestAndSet() argument
8 mov eax, Bit in InterlockedBitTestAndSet()
|
| /external/llvm/include/llvm/TableGen/ |
| D | Record.h | 343 virtual Init *getBit(unsigned Bit) const = 0;
417 Init *getBit(unsigned Bit) const override { in getBit() argument
444 Init *getBit(unsigned Bit) const override { in getBit() argument
445 assert(Bit < 1 && "Bit index out of range!"); in getBit()
501 Init *getBit(unsigned Bit) const override { in getBit() argument
502 assert(Bit < Bits.size() && "Bit index out of range!"); in getBit()
503 return Bits[Bit]; in getBit()
540 Init *getBit(unsigned Bit) const override { in getBit() argument
541 return BitInit::get((Value & (1ULL << Bit)) != 0); in getBit()
577 Init *getBit(unsigned Bit) const override { in getBit() argument
[all …]
|
| /external/llvm/docs/CommandGuide/ |
| D | llvm-bcanalyzer.rst | 207 The total number of 32-bit integers encoded using the Variable Bit Rate
212 The total number of 64-bit integers encoded using the Variable Bit Rate encoding
218 the Variable Bit Rate encoding scheme.
223 integers had they not been compressed with the Variable Bit Rage encoding
228 The total number of bytes saved by using the Variable Bit Rate encoding scheme.
288 integers that use the Variable Bit Rate encoding scheme.
294 Bit Rate encoding scheme.
298 The total number of bytes saved in this function by using the Variable Bit
|
| /external/llvm/lib/Transforms/IPO/ |
| D | LowerBitSets.cpp | 178 unsigned Bit = 0; in allocate() local
180 if (BitAllocs[I] < BitAllocs[Bit]) in allocate()
181 Bit = I; in allocate()
183 AllocByteOffset = BitAllocs[Bit]; in allocate()
187 BitAllocs[Bit] = ReqSize; in allocate()
192 AllocMask = 1 << Bit; in allocate()
428 for (auto Bit : BSI.Bits) in createBitSetTest() local
429 Bits |= uint64_t(1) << Bit; in createBitSetTest()
515 Value *Bit = createBitSetTest(ThenB, BSI, BAI, BitOffset); in lowerBitSetCall() local
523 P->addIncoming(Bit, ThenB.GetInsertBlock()); in lowerBitSetCall()
|
| /external/clang/docs/ |
| D | ControlFlowIntegrityDesign.rst | 49 .. csv-table:: Bit Vectors for A, B, C
56 Bit vectors are represented in the object file as byte arrays. By loading
58 test bits from the bit set with a relatively short instruction sequence. Bit
112 Stripping Leading/Trailing Zeros in Bit Vectors
121 .. csv-table:: Bit Vectors for A, B, C
128 Short Inline Bit Vectors
195 those sub-hierarchies need to be (see "Stripping Leading/Trailing Zeros in Bit
270 Eliminating Bit Vector Checks for All-Ones Bit Vectors
366 we can normally apply the `Alignment`_ and `Eliminating Bit Vector Checks
367 for All-Ones Bit Vectors`_ optimizations thus simplifying the check at each
|
| /external/llvm/lib/Fuzzer/ |
| D | FuzzerMutate.cpp | 51 int Bit = Rand(8); in FlipRandomBit() local
52 char Mask = 1 << Bit; in FlipRandomBit()
54 if (X & (1 << Bit)) in FlipRandomBit()
|
| /external/llvm/lib/TableGen/ |
| D | Record.cpp | 303 if (auto *Bit = dyn_cast<BitInit>(getBit(i))) in convertInitializerTo() local
304 Result |= static_cast<int64_t>(Bit->getValue()) << i; in convertInitializerTo()
329 if (Init *Bit = getBit(e-i-1)) in getAsString() local
330 Result += Bit->getAsString(); in getAsString()
365 Init *Bit = CachedInit->getBit(CurBit->getBitNum()); in resolveReferences() local
366 NewBits[i] = fixBitInit(RV, CurBit, Bit); in resolveReferences()
383 Init *Bit = CurBitVar->getBit(CurBit->getBitNum()); in resolveReferences() local
384 NewBits[i] = fixBitInit(RV, CurBit, Bit); in resolveReferences()
600 Init *OpInit::getBit(unsigned Bit) const { in getBit()
603 return VarBitInit::get(const_cast<OpInit*>(this), Bit); in getBit()
[all …]
|
| D | TGLexer.h | 46 Bit, Bits, Class, Code, Dag, Def, Foreach, Defm, Field, In, Int, Let, List, enumerator
|
| /external/llvm/lib/DebugInfo/DWARF/ |
| D | DWARFDebugInfoEntry.cpp | 85 uint64_t Bit = 1ULL << Shift; in dumpApplePropertyAttribute() local
86 if (const char *PropName = ApplePropertyString(Bit)) in dumpApplePropertyAttribute()
89 OS << format("DW_APPLE_PROPERTY_0x%" PRIx64, Bit); in dumpApplePropertyAttribute()
90 if (!(Val ^= Bit)) in dumpApplePropertyAttribute()
|
| /external/v8/test/cctest/ |
| D | test-assembler-arm64.cc | 6017 masm.FPTmpList()->set_list(d0.Bit()); in TEST()
6039 masm.FPTmpList()->set_list(d0.Bit()); in TEST()
8278 CHECK(x0.Bit() == (1UL << 0)); in TEST()
8279 CHECK(x1.Bit() == (1UL << 1)); in TEST()
8280 CHECK(x10.Bit() == (1UL << 10)); in TEST()
8283 CHECK(fp.Bit() == (1UL << kFramePointerRegCode)); in TEST()
8284 CHECK(lr.Bit() == (1UL << kLinkRegCode)); in TEST()
8287 CHECK(xzr.Bit() == (1UL << kZeroRegCode)); in TEST()
8290 CHECK(jssp.Bit() == (1UL << kJSSPCode)); in TEST()
8291 CHECK(csp.Bit() == (1UL << kSPRegInternalCode)); in TEST()
[all …]
|
| /external/antlr/antlr-3.4/runtime/ObjC/Framework/test/runtime/sets/ |
| D | ANTLRBitSetTest.m | 69 STAssertTrue([bitSet member:1], @"Bit at index 1 is not a member...");
73 STAssertFalse([bitSet member:1], @"Bit at index 1 is a member...");
|
| /external/llvm/lib/Target/X86/Utils/ |
| D | X86ShuffleDecode.cpp | 376 int Bit = NumElements > 8 ? i % (128 / ElementBits) : i; in DecodeBLENDMask() local
377 assert(Bit < 8 && in DecodeBLENDMask()
379 ShuffleMask.push_back(((Imm >> Bit) & 1) ? NumElements + i : i); in DecodeBLENDMask()
|
| /external/clang/include/clang/Basic/ |
| D | BuiltinsAArch64.def | 26 // Bit manipulation
|