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Searched refs:ByteAccess (Results 1 – 6 of 6) sorted by relevance

/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonBaseInfo.h96 ByteAccess = 1, // Byte access instruction (memb). enumerator
DHexagonMCCodeEmitter.cpp341 case HexagonII::MemAccessSize::ByteAccess: in getFixupNoBits()
/external/llvm/lib/Target/Hexagon/
DHexagonIsetDx.td79 let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in
148 let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in
422 let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in
480 let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in
680 let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in
DHexagonInstrInfoV4.td416 let accessSize = ByteAccess, hasNewValue = 1 in {
439 let accessSize = ByteAccess in
472 let accessSize = ByteAccess in {
615 let hasNewValue = 1, accessSize = ByteAccess in {
713 def S4_storerb_ap : T_ST_absset <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
750 def S4_storerbnew_ap : T_ST_absset_nv <"memb", "STrib", 0b00, ByteAccess>;
788 def S4_storerb_ur : T_StoreAbsReg <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
847 def S4_storerbnew_ur : T_StoreAbsRegNV <"memb", "STrib", 0b00, ByteAccess>;
1019 let accessSize = ByteAccess in
1154 let accessSize = ByteAccess in
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DHexagonInstrInfo.td1709 let accessSize = ByteAccess in {
1763 let accessSize = ByteAccess, opExtentBits = 11 in
1903 let accessSize = ByteAccess in {
1962 let accessSize = ByteAccess in
1995 def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>;
1996 def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>;
2049 let accessSize = ByteAccess in {
2096 def L2_loadalignb_pcr : T_loadalign_pcr <"memb_fifo", 0b0100, ByteAccess>;
2133 let accessSize = ByteAccess in {
2183 let accessSize = ByteAccess in
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DHexagonInstrFormats.td58 def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).