| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 446 case ISD::CONCAT_VECTORS: in ScalarizeVectorOperand()
599 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; in SplitVectorResult()
818 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps); in SplitVecRes_CONCAT_VECTORS()
821 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps); in SplitVecRes_CONCAT_VECTORS()
1406 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; in SplitVectorOperand()
1500 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect); in SplitVecOp_VSELECT()
1517 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
1676 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo, in SplitVecOp_MGATHER()
1920 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo, in SplitVecOp_TruncateHelper()
1948 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes); in SplitVecOp_VSETCC()
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| D | DAGCombiner.cpp | 1438 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); in visit()
5225 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
5226 RHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
5266 ISD::CONCAT_VECTORS, dl, VT, in ConvertSelectToConcatVector()
5477 SDValue GatherRes = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi); in visitMGATHER()
5561 SDValue LoadRes = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi); in visitMLOAD()
5634 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi); in visitVSELECT()
5647 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
5648 N2.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
5945 SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads); in CombineExtLoad()
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| D | SelectionDAGDumper.cpp | 219 case ISD::CONCAT_VECTORS: return "concat_vectors"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 102 case ISD::CONCAT_VECTORS: in PromoteIntegerResult()
719 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2); in PromoteIntRes_TRUNCATE()
883 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; in PromoteIntegerOperand()
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| D | SelectionDAGBuilder.cpp | 301 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS in getCopyFromPartsVector()
2735 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(), in visitShuffleVector()
2743 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(), in visitShuffleVector()
2760 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, in visitShuffleVector()
2762 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, in visitShuffleVector()
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| D | SelectionDAG.cpp | 3016 case ISD::CONCAT_VECTORS: in getNode()
3429 case ISD::CONCAT_VECTORS: in getNode()
3649 N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
3914 case ISD::CONCAT_VECTORS: in getNode()
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| D | LegalizeDAG.cpp | 3200 case ISD::CONCAT_VECTORS: { in ExpandNode()
4483 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps); in PromoteNode()
4606 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts); in PromoteNode()
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| /external/llvm/test/CodeGen/X86/ |
| D | widen_shuffle-1.ll | 68 ; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS
81 ; PR11389: another CONCAT_VECTORS case
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 283 CONCAT_VECTORS, enumerator
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1769 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE in HexagonTargetLowering()
1796 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom); in HexagonTargetLowering()
1812 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom); in HexagonTargetLowering()
1813 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i16, Custom); in HexagonTargetLowering()
1814 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32, Custom); in HexagonTargetLowering()
1815 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i64, Custom); in HexagonTargetLowering()
1817 setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom); in HexagonTargetLowering()
1818 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom); in HexagonTargetLowering()
1819 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32, Custom); in HexagonTargetLowering()
1820 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i64, Custom); in HexagonTargetLowering()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 171 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); in AMDGPUTargetLowering()
172 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom); in AMDGPUTargetLowering()
173 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); in AMDGPUTargetLowering()
174 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); in AMDGPUTargetLowering()
619 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
1250 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad), in SplitVectorLoad()
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| D | SIISelLowering.cpp | 218 case ISD::CONCAT_VECTORS: in SITargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 1287 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in X86TargetLowering()
1468 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom); in X86TargetLowering()
1469 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom); in X86TargetLowering()
1470 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom); in X86TargetLowering()
1471 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom); in X86TargetLowering()
1472 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom); in X86TargetLowering()
1636 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom); in X86TargetLowering()
1637 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom); in X86TargetLowering()
1638 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom); in X86TargetLowering()
1639 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom); in X86TargetLowering()
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| D | X86IntrinsicsInfo.h | 344 X86_INTRINSIC_DATA(avx512_kunpck_bw, KUNPCK, ISD::CONCAT_VECTORS, 0),
345 X86_INTRINSIC_DATA(avx512_kunpck_dq, KUNPCK, ISD::CONCAT_VECTORS, 0),
346 X86_INTRINSIC_DATA(avx512_kunpck_wd, KUNPCK, ISD::CONCAT_VECTORS, 0),
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| /external/llvm/test/CodeGen/ARM/ |
| D | vector-DAGCombine.ll | 31 ; Check CONCAT_VECTORS DAG combiner pass doesn't introduce illegal types.
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 494 setTargetDAGCombine(ISD::CONCAT_VECTORS); in AArch64TargetLowering()
673 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); in addTypeForNEON()
4924 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5300 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1); in tryFormConcatFromShuffle()
5438 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst); in GenerateTBL()
5446 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst); in GenerateTBL()
5524 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) { in LowerVECTOR_SHUFFLE()
7965 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy, in performConcatVectorsCombine()
8529 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in performExtendCombine()
9630 case ISD::CONCAT_VECTORS: in PerformDAGCombine()
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| D | AArch64InstrFormats.td | 7870 // intrinsic, represented by CONCAT_VECTORS.
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 116 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
5665 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
6024 if (V1->getOpcode() == ISD::CONCAT_VECTORS && in LowerVECTOR_SHUFFLE()
6043 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0), in LowerVECTOR_SHUFFLE()
6525 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
6561 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
6874 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
9443 if (Op0.getOpcode() != ISD::CONCAT_VECTORS || in PerformVECTOR_SHUFFLECombine()
9444 Op1.getOpcode() != ISD::CONCAT_VECTORS || in PerformVECTOR_SHUFFLECombine()
9461 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, in PerformVECTOR_SHUFFLECombine()
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| D | ARMISelDAGToDAG.cpp | 3347 case ISD::CONCAT_VECTORS: in Select()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 787 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); in initActions()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 542 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 680 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand); in PPCTargetLowering()
730 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand); in PPCTargetLowering()
772 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand); in PPCTargetLowering()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 1823 case ISD::CONCAT_VECTORS: in LowerOperation()
|