| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenExtract.cpp | 87 ConstantInt *CSL = 0, *CSR = 0, *CM = 0; in INITIALIZE_PASS_DEPENDENCY() local
94 bool Match = match(In, m_And(m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
101 Match = match(In, m_And(m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
108 CSR = ConstantInt::get(Type::getInt32Ty(Ctx), 0); in INITIALIZE_PASS_DEPENDENCY()
118 Match = match(In, m_And(m_LShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
125 Match = match(In, m_And(m_AShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
132 Match = match(In, m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
139 Match = match(In, m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
152 uint32_t SR = CSR->getZExtValue(); in INITIALIZE_PASS_DEPENDENCY()
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| D | HexagonVLIWPacketizer.cpp | 316 for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR) in doesModifyCalleeSavedReg() local
317 if (MI->modifiesRegister(*CSR, TRI)) in doesModifyCalleeSavedReg()
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| D | HexagonFrameLowering.cpp | 232 bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR) { in needsStackFrame() argument
261 if (CSR[R]) in needsStackFrame()
331 BitVector CSR(Hexagon::NUM_TARGET_REGS); in findShrunkPrologEpilog() local
333 CSR[*P] = true; in findShrunkPrologEpilog()
336 if (needsStackFrame(I, CSR)) in findShrunkPrologEpilog()
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| /external/llvm/lib/Target/X86/ |
| D | X86MachineFunctionInfo.cpp | 23 for (const MCPhysReg *CSR = in setRestoreBasePointer() local
25 unsigned Reg = *CSR; in setRestoreBasePointer()
26 ++CSR) in setRestoreBasePointer()
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| /external/llvm/lib/CodeGen/ |
| D | LivePhysRegs.cpp | 143 for (const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR) in addPristines() local
144 LiveRegs.addReg(*CSR); in addPristines()
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| D | RegisterClassInfo.cpp | 51 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); in runOnMachineFunction() local
52 if (Update || CSR != CalleeSaved) { in runOnMachineFunction()
57 for (unsigned N = 0; unsigned Reg = CSR[N]; ++N) in runOnMachineFunction()
62 CalleeSaved = CSR; in runOnMachineFunction()
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| D | MachineFunction.cpp | 619 for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR) in getPristineRegs() local
620 BV.set(*CSR); in getPristineRegs()
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| D | RegAllocPBQP.cpp | 547 const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF); in isACalleeSavedRegister() local
548 for (unsigned i = 0; CSR[i] != 0; ++i) in isACalleeSavedRegister()
549 if (TRI.regsOverlap(reg, CSR[i])) in isACalleeSavedRegister()
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| D | RegAllocGreedy.cpp | 845 unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg); in isUnusedCalleeSavedReg() local
846 if (CSR == 0) in isUnusedCalleeSavedReg()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFCallingConv.td | 29 def CSR : CalleeSavedRegs<(add R6, R7, R8, R9, R10)>;
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| /external/llvm/test/CodeGen/X86/ |
| D | catchpad-realign-savexmm.ll | 4 ; CSR save.
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| D | x86-shrink-wrapping.ll | 79 ; Make sure we save the CSR used in the inline asm: rbx.
156 ; Make sure we save the CSR used in the inline asm: rbx.
205 ; Make sure we save the CSR used in the inline asm: rbx.
283 ; Make sure we save the CSR used in the inline asm: rbx.
367 ; Make sure we save the CSR used in the inline asm: rbx.
734 ; In this case, the RegMask does not touch a CSR so we are good to go!
777 ; Clobber a CSR so that we check something on the regmask
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| D | x86-win64-shrink-wrapping.ll | 57 ; Make sure we save the CSR used in the inline asm: rbx.
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| /external/llvm/test/CodeGen/ARM/ |
| D | arm-shrink-wrapping.ll | 91 ; Make sure we save the CSR used in the inline asm: r4.
164 ; Make sure we save the CSR used in the inline asm: r4.
215 ; Make sure we save the CSR used in the inline asm: r4.
294 ; Make sure we save the CSR used in the inline asm: r4.
379 ; Make sure we save the CSR used in the inline asm: r4.
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| D | 2011-08-25-ldmia_ret.ll | 44 ; Fold the CSR+return into a pop
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| /external/llvm/test/CodeGen/Thumb/ |
| D | thumb-shrink-wrapping.ll | 126 ; Make sure we save the CSR used in the inline asm: r4.
201 ; Make sure we save the CSR used in the inline asm: r4.
252 ; Make sure we save the CSR used in the inline asm: r4.
336 ; Make sure we save the CSR used in the inline asm: r4.
426 ; Make sure we save the CSR used in the inline asm: r4.
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| /external/llvm/include/llvm/ADT/ |
| D | Triple.h | 129 CSR, enumerator
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | ppc-shrink-wrapping.ll | 376 ; Make sure we save the CSR used in the inline asm: r14
632 ; CHECK: std [[CSR:[0-9]+]], -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
635 ; CHECK: ld [[CSR]], -[[STACK_OFFSET]](1) # 8-byte Folded Reload
638 ; CHECK-NOT: {{[a-z]+}} [[CSR]]
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-shrink-wrapping.ll | 16 ; CHECK: stp [[SAVE_SP:x[0-9]+]], [[CSR:x[0-9]+]], [sp, #-16]!
37 ; CHECK-NEXT: ldp [[SAVE_SP]], [[CSR]], [sp], #16
407 ; Make sure we save the CSR used in the inline asm: x19.
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcCallingConv.td | 136 def CSR : CalleeSavedRegs<(add)> {
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| /external/llvm/lib/Support/ |
| D | Triple.cpp | 149 case CSR: return "csr"; in getVendorTypeName()
409 .Case("csr", Triple::CSR) in parseVendor()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 195 // Allocate LR as the first CSR since it is always saved anyway.
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| /external/clang/lib/Sema/ |
| D | SemaChecking.cpp | 4421 const CharSourceRange &CSR = getSpecifierRange(StartSpecifier, in checkFormatExpr() local
4436 << IsEnum << CSR << E->getSourceRange(), in checkFormatExpr()
4437 E->getLocStart(), /*IsStringLocation*/ false, CSR); in checkFormatExpr()
4448 << CSR in checkFormatExpr()
4450 E->getLocStart(), /*IsStringLocation*/false, CSR); in checkFormatExpr()
4462 << CSR in checkFormatExpr()
4464 E->getLocStart(), /*IsStringLocation*/false, CSR); in checkFormatExpr()
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| /external/harfbuzz_ng/src/ |
| D | hb-ot-shape-complex-indic-table.cc | 357 /* 17C8 */ _(M,R), _(RS,T), _(RS,T), _(SM,T),_(CSR,T), _(CK,T), _(SM,T), _(SM,T),
438 /* 1B00 */ _(Bi,T), _(Bi,T), _(Bi,T),_(CSR,T), _(Vs,R), _(VI,x), _(VI,x), _(VI,x),
457 /* 1B80 */ _(Bi,T),_(CSR,T), _(Vs,R), _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x),
590 /* A980 */ _(Bi,T), _(Bi,T),_(CSR,T), _(Vs,R), _(VI,x), _(VI,x), _(VI,x), _(VI,x),
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| /external/llvm/include/llvm/Target/ |
| D | Target.td | 229 // (and GPR, CSR) - Set intersection. All registers from the first set that are
|