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Searched refs:DST (Results 1 – 25 of 98) sorted by relevance

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/external/mesa3d/src/mesa/main/
Dmacros.h208 #define ZERO_4V( DST ) (DST)[0] = (DST)[1] = (DST)[2] = (DST)[3] = 0 argument
229 #define COPY_4V( DST, SRC ) \ argument
231 (DST)[0] = (SRC)[0]; \
232 (DST)[1] = (SRC)[1]; \
233 (DST)[2] = (SRC)[2]; \
234 (DST)[3] = (SRC)[3]; \
258 #define COPY_SZ_4V(DST, SZ, SRC) \ argument
261 case 4: (DST)[3] = (SRC)[3]; \
262 case 3: (DST)[2] = (SRC)[2]; \
263 case 2: (DST)[1] = (SRC)[1]; \
[all …]
/external/bison/lib/
Dbitset.h193 #define bitset_ones(DST) BITSET_ONES_ (DST) argument
196 #define bitset_zero(DST) BITSET_ZERO_ (DST) argument
201 #define bitset_copy(DST, SRC) BITSET_COPY_ (DST, SRC) argument
204 #define bitset_disjoint_p(DST, SRC) BITSET_DISJOINT_P_ (DST, SRC) argument
207 #define bitset_equal_p(DST, SRC) BITSET_EQUAL_P_ (DST, SRC) argument
210 #define bitset_not(DST, SRC) BITSET_NOT_ (DST, SRC) argument
213 #define bitset_subset_p(DST, SRC) BITSET_SUBSET_P_ (DST, SRC) argument
218 #define bitset_and(DST, SRC1, SRC2) BITSET_AND_ (DST, SRC1, SRC2) argument
221 #define bitset_and_cmp(DST, SRC1, SRC2) BITSET_AND_CMP_ (DST, SRC1, SRC2) argument
224 #define bitset_andn(DST, SRC1, SRC2) BITSET_ANDN_ (DST, SRC1, SRC2) argument
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Dbbitset.h161 #define BITSET_CHECK2_(DST, SRC) \ argument
162 if (!BITSET_COMPATIBLE_ (DST, SRC)) abort ();
164 #define BITSET_CHECK3_(DST, SRC1, SRC2) \ argument
165 if (!BITSET_COMPATIBLE_ (DST, SRC1) \
166 || !BITSET_COMPATIBLE_ (DST, SRC2)) abort ();
168 #define BITSET_CHECK4_(DST, SRC1, SRC2, SRC3) \ argument
169 if (!BITSET_COMPATIBLE_ (DST, SRC1) || !BITSET_COMPATIBLE_ (DST, SRC2) \
170 || !BITSET_COMPATIBLE_ (DST, SRC3)) abort ();
174 #define BITSET_RESIZE_(DST, SIZE) (DST)->b.vtable->resize (DST, SIZE) argument
183 #define BITSET_TYPE_(DST) (DST)->b.vtable->type argument
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/external/libvpx/libvpx/vpx_dsp/
Dintrapred.c17 #define DST(x, y) dst[(x) + (y) * stride] macro
331 DST(0, 0) = AVG2(I, J); in vpx_d207_predictor_4x4_c()
332 DST(2, 0) = DST(0, 1) = AVG2(J, K); in vpx_d207_predictor_4x4_c()
333 DST(2, 1) = DST(0, 2) = AVG2(K, L); in vpx_d207_predictor_4x4_c()
334 DST(1, 0) = AVG3(I, J, K); in vpx_d207_predictor_4x4_c()
335 DST(3, 0) = DST(1, 1) = AVG3(J, K, L); in vpx_d207_predictor_4x4_c()
336 DST(3, 1) = DST(1, 2) = AVG3(K, L, L); in vpx_d207_predictor_4x4_c()
337 DST(3, 2) = DST(2, 2) = in vpx_d207_predictor_4x4_c()
338 DST(0, 3) = DST(1, 3) = DST(2, 3) = DST(3, 3) = L; in vpx_d207_predictor_4x4_c()
351 DST(0, 0) = AVG2(A, B); in vpx_d63_predictor_4x4_c()
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/external/webp/src/dsp/
Denc.c337 #define DST(x, y) dst[(x) + (y) * BPS] macro
383 DST(0, 3) = AVG3(J, K, L); in RD4()
384 DST(0, 2) = DST(1, 3) = AVG3(I, J, K); in RD4()
385 DST(0, 1) = DST(1, 2) = DST(2, 3) = AVG3(X, I, J); in RD4()
386 DST(0, 0) = DST(1, 1) = DST(2, 2) = DST(3, 3) = AVG3(A, X, I); in RD4()
387 DST(1, 0) = DST(2, 1) = DST(3, 2) = AVG3(B, A, X); in RD4()
388 DST(2, 0) = DST(3, 1) = AVG3(C, B, A); in RD4()
389 DST(3, 0) = AVG3(D, C, B); in RD4()
401 DST(0, 0) = AVG3(A, B, C); in LD4()
402 DST(1, 0) = DST(0, 1) = AVG3(B, C, D); in LD4()
[all …]
Ddec.c161 #define DST(x, y) dst[(x) + (y) * BPS] macro
288 DST(0, 3) = AVG3(J, K, L); in RD4()
289 DST(1, 3) = DST(0, 2) = AVG3(I, J, K); in RD4()
290 DST(2, 3) = DST(1, 2) = DST(0, 1) = AVG3(X, I, J); in RD4()
291 DST(3, 3) = DST(2, 2) = DST(1, 1) = DST(0, 0) = AVG3(A, X, I); in RD4()
292 DST(3, 2) = DST(2, 1) = DST(1, 0) = AVG3(B, A, X); in RD4()
293 DST(3, 1) = DST(2, 0) = AVG3(C, B, A); in RD4()
294 DST(3, 0) = AVG3(D, C, B); in RD4()
306 DST(0, 0) = AVG3(A, B, C); in LD4()
307 DST(1, 0) = DST(0, 1) = AVG3(B, C, D); in LD4()
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Denc_sse2.c789 #define DST(x, y) dst[(x) + (y) * BPS] macro
874 DST(0, 2) = AVG3(J, I, X); in VR4()
875 DST(0, 3) = AVG3(K, J, I); in VR4()
900 DST(3, 2) = (extra_out >> 0) & 0xff; in VL4()
901 DST(3, 3) = (extra_out >> 8) & 0xff; in VL4()
925 DST(0, 0) = AVG2(I, J); in HU4()
926 DST(2, 0) = DST(0, 1) = AVG2(J, K); in HU4()
927 DST(2, 1) = DST(0, 2) = AVG2(K, L); in HU4()
928 DST(1, 0) = AVG3(I, J, K); in HU4()
929 DST(3, 0) = DST(1, 1) = AVG3(J, K, L); in HU4()
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Ddec_mips_dsp_r2.c625 #define STORE_8_BYTES(TEMP0, TEMP1, A, B, C, DST) \ argument
626 "usw %[" #TEMP0 "], " #A "*" XSTR(BPS) "(%[" #DST "]) \n\t" \
627 "usw %[" #TEMP1 "], " #B "+" #C "*" XSTR(BPS) "(%[" #DST "]) \n\t"
898 #define CLIP_8B_TO_DST(DST, TOP, SIZE) do { \ argument
899 int dst_1 = ((int)(DST)[-1] << 16) + (DST)[-1]; \
924 : [top_1]"r"(top_1), [top]"r"((TOP)), [dst]"r"((DST)) \
929 #define CLIP_TO_DST(DST, SIZE) do { \ argument
931 const uint8_t* top = (DST) - BPS; \
934 CLIP_8B_TO_DST((DST), top, (SIZE)); \
935 (DST) += BPS; \
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Denc_mips_dsp_r2.c339 #define FILL_8_OR_16(DST, VALUE, SIZE) do { \ argument
362 : [dst]"r"((DST)) \
367 #define VERTICAL_PRED(DST, TOP, SIZE) \ argument
368 static WEBP_INLINE void VerticalPred##SIZE(uint8_t* (DST), \
372 for (j = 0; j < (SIZE); ++j) memcpy((DST) + j * BPS, (TOP), (SIZE)); \
374 FILL_8_OR_16((DST), 127, (SIZE)); \
383 #define HORIZONTAL_PRED(DST, LEFT, SIZE) \ argument
384 static WEBP_INLINE void HorizontalPred##SIZE(uint8_t* (DST), \
389 memset((DST) + j * BPS, (LEFT)[j], (SIZE)); \
392 FILL_8_OR_16((DST), 129, (SIZE)); \
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Dfilters_mips_dsp_r2.c40 #define DO_PREDICT_LINE(SRC, DST, LENGTH, INVERSE) do { \ argument
42 uint8_t* pdst = (uint8_t*)(DST); \
116 #define DO_PREDICT_LINE_VERTICAL(SRC, PRED, DST, LENGTH, INVERSE) do { \ argument
119 uint8_t* pdst = (uint8_t*)(DST); \
175 #define PREDICT_LINE_ONE_PASS(SRC, PRED, DST, INVERSE) do { \ argument
187 : [pred]"r"((PRED)), [dst]"r"((DST)), [src]"r"((SRC)) \
Drescaler_neon.c26 #define LOAD_32x4(SRC, DST) const uint32x4_t DST = vld1q_u32((SRC)) argument
31 #define STORE_32x8(SRC0, SRC1, DST) do { \ argument
32 vst1q_u32((DST) + 0, SRC0); \
33 vst1q_u32((DST) + 4, SRC1); \
/external/v8/src/
Ddate.h230 struct DST { struct
250 DST* LeastRecentlyUsedDST(DST* skip);
257 inline void ClearSegment(DST* segment);
259 bool InvalidSegment(DST* segment) { in InvalidSegment()
266 DST dst_[kDSTSize];
268 DST* before_;
269 DST* after_;
Ddate.cc45 void DateCache::ClearSegment(DST* segment) { in ClearSegment()
261 DST* temp = before_; in DaylightSavingsOffsetInMs()
310 DST* temp = before_; in DaylightSavingsOffsetInMs()
323 DST* before = NULL; in ProbeDST()
324 DST* after = NULL; in ProbeDST()
362 DateCache::DST* DateCache::LeastRecentlyUsedDST(DST* skip) { in LeastRecentlyUsedDST()
363 DST* result = NULL; in LeastRecentlyUsedDST()
/external/mesa3d/src/mesa/swrast/
Ds_chan.h79 #define COPY_CHAN4(DST, SRC) COPY_4UBV(DST, SRC) argument
91 #define COPY_CHAN4(DST, SRC) COPY_4V(DST, SRC) argument
103 #define COPY_CHAN4(DST, SRC) COPY_4V(DST, SRC) argument
/external/deqp/framework/common/
DtcuInterval.hpp174 #define TCU_SET_INTERVAL_BOUNDS(DST, VAR, SETLOW, SETHIGH) do \ argument
177 ::tcu::Interval& VAR##_dst_ = (DST); \
195 #define TCU_SET_INTERVAL(DST, VAR, BODY) \ argument
196 TCU_SET_INTERVAL_BOUNDS(DST, VAR, BODY, BODY)
203 #define TCU_INTERVAL_APPLY_MONOTONE1(DST, PARAM, ARG, VAR, BODY) do \ argument
206 ::tcu::Interval& VAR##_dst_ = (DST); \
229 #define TCU_INTERVAL_APPLY_MONOTONE2(DST, P0, A0, P1, A1, VAR, BODY) \ argument
231 DST, P0, A0, tmp2_, \
234 #define TCU_INTERVAL_APPLY_MONOTONE3(DST, P0, A0, P1, A1, P2, A2, VAR, BODY) \ argument
236 DST, P0, A0, tmp3_, \
/external/mesa3d/src/gallium/auxiliary/util/
Du_math.h728 #define COPY_4V( DST, SRC ) \ argument
730 (DST)[0] = (SRC)[0]; \
731 (DST)[1] = (SRC)[1]; \
732 (DST)[2] = (SRC)[2]; \
733 (DST)[3] = (SRC)[3]; \
739 #define COPY_4FV( DST, SRC ) COPY_4V(DST, SRC) argument
744 #define ASSIGN_4V( DST, V0, V1, V2, V3 ) \ argument
746 (DST)[0] = (V0); \
747 (DST)[1] = (V1); \
748 (DST)[2] = (V2); \
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/external/chromium-trace/catapult/third_party/gsutil/third_party/httplib2/
DMakefile13 DST = dist/httplib2-$(VERSION) macro
31 cp -r python2 $(DST)
32 cp -r python3 $(DST)
33 cp setup.py README MANIFEST.in CHANGELOG $(DST)
/external/llvm/test/CodeGen/AMDGPU/
Dbfi_int.ll40 ; R600: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], KC0[2].Z, KC0[2].W
41 ; R600: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, KC0[3].X, KC0[2].W
42 ; SI: v_xor_b32_e32 [[DST:v[0-9]+]], {{s[0-9]+, v[0-9]+}}
43 ; SI: v_bfi_b32 {{v[0-9]+}}, [[DST]], {{s[0-9]+, v[0-9]+}}
Dvertex-fetch-encoding.ll17 ; NI: VTX_READ_128 T[[DST:[0-9]]].XYZW, T[[SRC:[0-9]]].X, 0 ; encoding: [0x40,0x01,0x0[[SRC]],0x40,…
Dload.ll23 ; R600: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
24 ; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
121 ; R600: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]]
122 ; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
313 ; R600: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
314 ; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
352 ; R600: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]]
353 ; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp320 SDValue DST; in LowerSDIV() local
322 DST = LowerSDIV64(Op, DAG); in LowerSDIV()
324 DST = LowerSDIV32(Op, DAG); in LowerSDIV()
327 DST = LowerSDIV24(Op, DAG); in LowerSDIV()
329 DST = SDValue(Op.getNode(), 0); in LowerSDIV()
331 return DST; in LowerSDIV()
338 SDValue DST; in LowerSREM() local
340 DST = LowerSREM64(Op, DAG); in LowerSREM()
342 DST = LowerSREM32(Op, DAG); in LowerSREM()
344 DST = LowerSREM16(Op, DAG); in LowerSREM()
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/external/llvm/test/Transforms/MemCpyOpt/
Dmemset-memcpy-redundant-memset.ll6 ; CHECK-DAG: [[DST:%[0-9]+]] = getelementptr i8, i8* %dst, i64 %src_size
10 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* [[DST]], i8 %c, i64 [[SIZE]], i32 1, i1 false)
21 ; CHECK-DAG: [[DST:%[0-9]+]] = getelementptr i8, i8* %dst, i64 %src_size
25 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* [[DST]], i8 %c, i64 [[SIZE]], i32 1, i1 false)
36 ; CHECK-DAG: [[DST:%[0-9]+]] = getelementptr i8, i8* %dst, i128 [[SRCSIZE]]
40 ; CHECK-NEXT: call void @llvm.memset.p0i8.i128(i8* [[DST]], i8 %c, i128 [[SIZE]], i32 1, i1 false)
51 ; CHECK-DAG: [[DST:%[0-9]+]] = getelementptr i8, i8* %dst, i128 %src_size
55 ; CHECK-NEXT: call void @llvm.memset.p0i8.i128(i8* [[DST]], i8 %c, i128 [[SIZE]], i32 1, i1 false)
66 ; CHECK-DAG: [[DST:%[0-9]+]] = getelementptr i8, i8* %dst, i64 [[SRCSIZE]]
70 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* [[DST]], i8 %c, i64 [[SIZE]], i32 1, i1 false)
[all …]
/external/mesa3d/src/mesa/x86/
Dsse_xform4.S36 #define DST(i) REGOFF(i * 4, EDI) macro
97 MOVAPS( XMM0, DST(0) ) /* ->D(3) | ->D(2) | ->D(1) | ->D(0) */
169 MOVAPS( XMM4, DST(0) ) /* ->D(3) | ->D(2) | ->D(1) | ->D(0) */
172 MOVSS( XMM4, DST(3) ) /* ->D(3) */
/external/mesa3d/src/gallium/auxiliary/draw/
Ddraw_pipe_flatshade.c51 #define COPY_3FV( DST, SRC ) \ argument
53 (DST)[0] = (SRC)[0]; \
54 (DST)[1] = (SRC)[1]; \
55 (DST)[2] = (SRC)[2]; \
/external/iproute2/examples/
Dcbq.init-v0.7.3810 SRC=${rule%%,*}; DST=${rule##*,}
815 DADDR=${DST%%:*}; DTEMP=${DST##*:}
816 [ "$DADDR" = "$DST" ] && DTEMP=""

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