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Searched refs:Defs (Results 1 – 25 of 126) sorted by relevance

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/external/lzma/CPP/7zip/Archive/7z/
D7zItem.h95 CBoolVector Defs; member
100 Defs.ClearAndSetSize(newSize); in ClearAndSetSize()
106 Defs.Clear(); in Clear()
112 Defs.ReserveDown(); in ReserveDown()
116 bool ValidAndDefined(unsigned i) const { return i < Defs.Size() && Defs[i]; } in ValidAndDefined()
121 CBoolVector Defs; member
126 Defs.Clear(); in Clear()
132 Defs.ReserveDown(); in ReserveDown()
138 if (index < Defs.Size() && Defs[index]) in GetItem()
149 bool CheckSize(unsigned size) const { return Defs.Size() == size || Defs.Size() == 0; } in CheckSize()
D7zOut.cpp335 for (i = 0; i < digests.Defs.Size(); i++) in WriteHashDigests()
336 if (digests.Defs[i]) in WriteHashDigests()
342 if (numDefined == digests.Defs.Size()) in WriteHashDigests()
347 WriteBoolVector(digests.Defs); in WriteHashDigests()
349 for (i = 0; i < digests.Defs.Size(); i++) in WriteHashDigests()
350 if (digests.Defs[i]) in WriteHashDigests()
444 digests2.Defs.Add(digests.Defs[digestIndex]); in WriteSubStreamsInfo()
495 for (i = 0; i < v.Defs.Size(); i++) in WriteUInt64DefVector()
496 if (v.Defs[i]) in WriteUInt64DefVector()
502 WriteAlignedBoolHeader(v.Defs, numDefined, type, 8); in WriteUInt64DefVector()
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/external/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp63 BitVector Defs, Uses; member
64 DefUseInfo() : Defs(), Uses() {} in DefUseInfo()
65 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {} in DefUseInfo()
87 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
118 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, in getDefsUses() argument
125 expandReg(*R++, Defs); in getDefsUses()
135 BitVector &Set = Mo->isDef() ? Defs : Uses; in getDefsUses()
145 BitVector Defs(NR), Uses(NR); in buildMaps() local
150 Defs.reset(); in buildMaps()
152 getDefsUses(MI, Defs, Uses); in buildMaps()
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DHexagonInstrInfoV3.td24 let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, isPredicable = 1,
39 let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, isPredicated = 1,
67 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs in
80 let isCodeGenOnly = 1, Defs = VolatileV3.Regs in {
92 let Defs = [USR_OVF], Itinerary = ALU64_tc_2_SLOT23 in
193 let Defs = [USR_OVF], hasSideEffects = 0 in
222 let Defs = [USR_OVF], hasSideEffects = 0 in
265 let Defs = [P0], isPredicateLate = 1, Itinerary = S_3op_tc_1_SLOT23 in
DHexagonExpandCondsets.cpp166 bool canMoveOver(MachineInstr *MI, ReferenceMap &Defs, ReferenceMap &Uses);
292 SmallVector<MachineInstr*,8> Defs; in makeUndead() local
299 Defs.push_back(MI); in makeUndead()
303 Defs.push_back(MI); in makeUndead()
306 for (unsigned i = 0, n = Defs.size(); i < n; ++i) { in makeUndead()
307 MachineInstr *MI = Defs[i]; in makeUndead()
435 SmallVector<RegisterRef,2> Defs; in addInstrToLiveness() local
438 Defs.push_back(RegisterRef(Op)); in addInstrToLiveness()
440 for (unsigned i = 0, n = Defs.size(); i < n; ++i) { in addInstrToLiveness()
441 unsigned DefR = Defs[i].Reg; in addInstrToLiveness()
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DHexagonIsetDx.td32 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isBr…
42 let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAc…
53 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicated…
122 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, isBran…
180 let Defs = [P0], isCodeGenOnly = 1, hasSideEffects = 0 in
211 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1,…
221 let Defs = [R29, R30], Uses = [R30, R31, R29], isCodeGenOnly = 1, mayStore = 1, accessSize = Double…
277 let Defs = [PC], Uses = [R31], isCodeGenOnly = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffect…
536 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPr…
560 let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWo…
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DHexagonBitSimplify.cpp158 static void getInstrDefs(const MachineInstr &MI, RegisterSet &Defs);
227 RegisterSet Defs; in INITIALIZE_PASS_DEPENDENCY() local
229 getInstrDefs(I, Defs); in INITIALIZE_PASS_DEPENDENCY()
231 NewAVs.insert(Defs); in INITIALIZE_PASS_DEPENDENCY()
247 RegisterSet &Defs) { in getInstrDefs() argument
254 Defs.insert(R); in getInstrDefs()
1424 RegisterSet Defs; in processBlock() local
1429 Defs.clear(); in processBlock()
1430 HBS::getInstrDefs(*I, Defs); in processBlock()
1431 if (Defs.count() != 1) in processBlock()
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/external/llvm/lib/Target/ARM/
DThumb2ITBlockPass.cpp46 SmallSet<unsigned, 4> &Defs,
57 SmallSet<unsigned, 4> &Defs, in TrackDefUses() argument
87 Defs.insert(*Subreg); in TrackDefUses()
121 SmallSet<unsigned, 4> &Defs, in MoveCopyOutOfITBlock() argument
136 if (Uses.count(DstReg) || Defs.count(SrcReg)) in MoveCopyOutOfITBlock()
178 SmallSet<unsigned, 4> Defs; in InsertITInstructions() local
191 Defs.clear(); in InsertITInstructions()
193 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions()
234 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { in InsertITInstructions()
244 TrackDefUses(NMI, Defs, Uses, TRI); in InsertITInstructions()
/external/llvm/lib/Target/PowerPC/
DPPCBoolRetToInt.cpp62 SmallPtrSet<Value *, 8> Defs; in findAllDefs() local
65 Defs.insert(V); in findAllDefs()
71 if (Defs.insert(Op).second) in findAllDefs()
74 return Defs; in findAllDefs()
193 auto Defs = findAllDefs(U); in runOnUse() local
196 if (!std::any_of(Defs.begin(), Defs.end(), isa<Instruction, Value *>)) in runOnUse()
202 for (const auto &V : Defs) in runOnUse()
206 for (const auto &V : Defs) in runOnUse()
217 for (const auto &V : Defs) in runOnUse()
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td92 class Defs<list<Register> Regs> {
93 list<Register> Defs = Regs;
544 Defs<[DSPOutFlag20]>;
548 IsCommutable, Defs<[DSPOutFlag20]>;
552 Defs<[DSPOutFlag20]>;
556 Defs<[DSPOutFlag20]>;
560 Defs<[DSPOutFlag20]>;
564 IsCommutable, Defs<[DSPOutFlag20]>;
568 Defs<[DSPOutFlag20]>;
572 Defs<[DSPOutFlag20]>;
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DMicroMipsDSPInstrInfo.td170 "absq_s.ph", int_mips_absq_s_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
172 "absq_s.w", int_mips_absq_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag20]>;
174 "absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
208 Defs<[DSPOutFlag22]>;
211 Defs<[DSPOutFlag22]>;
214 Defs<[DSPOutFlag22]>;
217 Defs<[DSPOutFlag22]>;
242 "shllv.ph", int_mips_shll_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
245 Defs<[DSPOutFlag22]>;
247 "shllv.qb", int_mips_shll_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
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DMipsDelaySlotFiller.cpp96 BitVector Defs, Uses; member in __anon4295b7990111::RegDefsUses
160 SmallPtrSet<ValueType, 4> Uses, Defs; member in __anon4295b7990111::MemDefsUses
296 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {} in RegDefsUses()
305 Defs.set(Mips::RA); in init()
311 Defs.reset(Mips::AT); in init()
322 Defs.set(Mips::RA); in setCallerSaved()
323 Defs.set(Mips::RA_64); in setCallerSaved()
337 Defs |= CallerSavedRegs; in setCallerSaved()
350 Defs |= AllocSet.flip(); in setUnallocatableRegs()
373 Defs |= NewDefs; in update()
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCChecker.cpp40 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0? in init()
41 Defs[Hexagon::LC0].insert(Unconditional); in init()
44 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0? in init()
45 Defs[Hexagon::LC1].insert(Unconditional); in init()
113 Defs[R].insert(PredSense(PredReg, isTrue)); in init()
152 CurDefs.insert(*SRI), Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
165 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
330 if (!Defs.count(P) || LatePreds.count(P)) { in checkPredicates()
344 if (LatePreds.count(P) > 1 || Defs.count(P)) { in checkPredicates()
379 for (const auto& I : Defs) { in checkRegisters()
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/external/llvm/lib/CodeGen/
DMachineCopyPropagation.cpp72 const DestList& Defs = SI->second; in SourceNoLongerAvailable() local
73 for (DestList::const_iterator I = Defs.begin(), E = Defs.end(); in SourceNoLongerAvailable()
231 SmallVector<unsigned, 2> Defs; in CopyPropagateBlock() local
248 Defs.push_back(Reg); in CopyPropagateBlock()
268 Defs.push_back(Reg); in CopyPropagateBlock()
299 for (unsigned i = 0, e = Defs.size(); i != e; ++i) { in CopyPropagateBlock()
300 unsigned Reg = Defs[i]; in CopyPropagateBlock()
DLiveVariables.cpp444 SmallVectorImpl<unsigned> &Defs) { in HandlePhysRegDef() argument
483 Defs.push_back(Reg); // Remember this def. in HandlePhysRegDef()
487 SmallVectorImpl<unsigned> &Defs) { in UpdatePhysRegDefs() argument
488 while (!Defs.empty()) { in UpdatePhysRegDefs()
489 unsigned Reg = Defs.back(); in UpdatePhysRegDefs()
490 Defs.pop_back(); in UpdatePhysRegDefs()
501 SmallVectorImpl<unsigned> &Defs) { in runOnInstr() argument
558 HandlePhysRegDef(MOReg, MI, Defs); in runOnInstr()
560 UpdatePhysRegDefs(MI, Defs); in runOnInstr()
565 SmallVector<unsigned, 4> Defs; in runOnBlock() local
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DMachineInstrBundle.cpp134 SmallVector<MachineOperand*, 4> Defs; in finalizeBundle() local
141 Defs.push_back(&MO); in finalizeBundle()
166 for (unsigned i = 0, e = Defs.size(); i != e; ++i) { in finalizeBundle()
167 MachineOperand &MO = *Defs[i]; in finalizeBundle()
194 Defs.clear(); in finalizeBundle()
DRegisterPressure.cpp321 SmallVector<unsigned, 8> Defs; member in __anonc91adad50111::RegisterOperands
355 std::bind1st(std::ptr_fun(containsReg), RegOpers.Defs)); in collectInstr()
371 pushRegUnits(Reg, RegOpers.Defs); in collectOperand()
403 for (SmallVectorImpl<unsigned>::iterator RI = Defs.begin(); in detectDeadDefs()
404 RI != Defs.end(); /*empty*/) { in detectDeadDefs()
413 RI = Defs.erase(RI); in detectDeadDefs()
476 for (unsigned Reg : RegOpers.Defs) in collectPDiff()
557 for (unsigned Reg : RegOpers.Defs) { in recede()
583 for (unsigned Reg : RegOpers.Defs) { in recede()
635 for (unsigned Reg : RegOpers.Defs) { in advance()
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/external/lzma/C/
D7z.h77 Byte *Defs; /* MSB 0 bit numbering */ member
83 Byte *Defs; /* MSB 0 bit numbering */ member
90 #define SzBitWithVals_Check(p, i) ((p)->Defs && ((p)->Defs[(i) >> 3] & (0x80 >> ((i) & 7))) != 0)
/external/llvm/utils/TableGen/
DCTagsEmitter.cpp67 const auto &Defs = Records.getDefs(); in run() local
70 Tags.reserve(Classes.size() + Defs.size()); in run()
73 for (const auto &D : Defs) in run()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFloat.td15 let Defs = [ARGUMENTS] in {
39 } // Defs = [ARGUMENTS]
51 let Defs = [ARGUMENTS] in {
62 } // Defs = [ARGUMENTS]
78 let Defs = [ARGUMENTS] in {
87 } // Defs = [ARGUMENTS]
DWebAssemblyInstrControl.td15 let Defs = [ARGUMENTS] in {
32 } // Defs = [ARGUMENTS]
39 let Defs = [ARGUMENTS] in {
78 } // Defs = [ARGUMENTS]
DWebAssemblyInstrInteger.td15 let Defs = [ARGUMENTS] in {
57 } // Defs = [ARGUMENTS]
65 let Defs = [ARGUMENTS] in {
74 } // Defs = [ARGUMENTS]
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td57 // AL is really implied by AX, but the registers in Defs must match the
60 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
68 let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
73 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], hasSideEffects = 0 in
79 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
85 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
95 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
100 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
105 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
112 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
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/external/clang/utils/TableGen/
DNeonEmitter.cpp502 void genBuiltinsDef(raw_ostream &OS, SmallVectorImpl<Intrinsic *> &Defs);
504 SmallVectorImpl<Intrinsic *> &Defs);
506 SmallVectorImpl<Intrinsic *> &Defs);
1964 SmallVectorImpl<Intrinsic *> &Defs) { in genBuiltinsDef() argument
1971 for (auto *Def : Defs) { in genBuiltinsDef()
1995 SmallVectorImpl<Intrinsic *> &Defs) { in genOverloadTypeCheckCode() argument
2009 for (auto *Def : Defs) { in genOverloadTypeCheckCode()
2091 SmallVectorImpl<Intrinsic *> &Defs) { in genIntrinsicRangeCheckCode() argument
2096 for (auto *Def : Defs) { in genIntrinsicRangeCheckCode()
2177 SmallVector<Intrinsic *, 128> Defs; in runHeader() local
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/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.td83 let isBranch = 1, isTerminator = 1, Defs = [CC] in {
195 let Defs = [CC] in {
236 let isCall = 1, Defs = [R14D, CC] in {
254 let isCall = 1, Defs = [R14D, CC] in {
283 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
337 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
400 let mayLoad = 1, mayStore = 1, Defs = [CC] in
426 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
457 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
610 let Defs = [CC] in {
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