| /external/llvm/test/CodeGen/X86/ |
| D | fnabs.ll | 4 ; FNABS(x) operation -> FNEG (FABS(x)).
5 ; If the FABS() result isn't used, the AND instruction should be eliminated.
|
| /external/llvm/test/Transforms/InstCombine/ |
| D | pow-1.ll | 86 ; CHECK-NEXT: [[FABS:%[a-z0-9]+]] = call double @fabs(double [[SQRT]]) [[NUW_RO]]
88 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], double 0x7FF0000000000000, double [[FABS]]
166 ; CHECK-NEXT: [[FABS:%[a-z0-9]+]] = call double @fabs(double [[SQRT]])
168 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], double 0x7FF0000000000000, double [[FABS]]
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstructions.td | 103 class FABS <RegisterClass rc> : AMDGPUShaderInst <
106 "FABS $dst, $src0",
|
| D | AMDILISelLowering.cpp | 201 setOperationAction(ISD::FABS, MVT::f64, Expand); in InitAMDILLowering()
202 setOperationAction(ISD::FABS, MVT::v2f64, Expand); in InitAMDILLowering()
548 fr = DAG.getNode(ISD::FABS, DL, FLTTY, fr); in LowerSDIV24()
551 fb = DAG.getNode(ISD::FABS, DL, FLTTY, fb); in LowerSDIV24()
|
| D | AMDGPUISelLowering.cpp | 115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 515 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
|
| D | BasicTTIImpl.h | 642 ISD = ISD::FABS; in getIntrinsicInstrCost()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 1146 if ((Opc == ISD::FABS || Opc == ISD::FNEG) && !HST->hasV5TOps()) in SelectBitOp()
1150 if (Opc != ISD::FABS && Opc != ISD::FNEG) { in SelectBitOp()
1182 if (Opc != ISD::FABS && Opc != ISD::FNEG) { in SelectBitOp()
1200 case ISD::FABS: in SelectBitOp()
1251 if (Opc != ISD::FABS && Opc != ISD::FNEG) in SelectBitOp()
1333 case ISD::FABS: in Select()
|
| /external/v8/src/ppc/ |
| D | constants-ppc.h | 288 FABS = 264 << 1, // Floating Absolute Value enumerator
|
| D | disasm-ppc.cc | 1005 case FABS: { in DecodeExt4()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 76 case ISD::FABS: R = SoftenFloatRes_FABS(N, ResNo); break; in SoftenFloatResult()
784 case ISD::FABS: in CanSkipSoftenFloatOperand()
799 case ISD::FABS: in CanSkipSoftenFloatOperand()
998 case ISD::FABS: ExpandFloatRes_FABS(N, Lo, Hi); break; in ExpandFloatResult()
1058 Hi = DAG.getNode(ISD::FABS, dl, Tmp.getValueType(), Tmp); in ExpandFloatRes_FABS()
1851 case ISD::FABS: in PromoteFloatResult()
|
| D | SelectionDAGDumper.cpp | 152 case ISD::FABS: return "fabs"; in getOperationName()
|
| D | DAGCombiner.cpp | 1425 case ISD::FABS: return visitFABS(N); in visit()
7330 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) && in visitBITCAST()
7347 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
7365 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
8825 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) in visitFCOPYSIGN()
8826 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); in visitFCOPYSIGN()
8830 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0)); in visitFCOPYSIGN()
8837 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || in visitFCOPYSIGN()
8843 if (N1.getOpcode() == ISD::FABS) in visitFCOPYSIGN()
8844 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); in visitFCOPYSIGN()
[all …]
|
| D | LegalizeVectorOps.cpp | 301 case ISD::FABS: in LegalizeOp()
|
| D | LegalizeDAG.cpp | 1725 if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) && in ExpandFCOPYSIGN()
1727 SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag); in ExpandFCOPYSIGN()
3345 case ISD::FABS: in ExpandNode()
4451 case ISD::FABS: in PromoteNode()
|
| D | LegalizeVectorTypes.cpp | 77 case ISD::FABS: in ScalarizeVectorResult()
632 case ISD::FABS: in SplitVectorResult()
2090 case ISD::FABS: in WidenVectorResult()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructions.td | 459 class FABS <RegisterClass rc> : AMDGPUShaderInst <
462 "FABS $dst, $src0",
|
| D | AMDGPUISelLowering.cpp | 88 setOperationAction(ISD::FABS, MVT::f32, Legal); in AMDGPUTargetLowering()
341 setOperationAction(ISD::FABS, VT, Expand); in AMDGPUTargetLowering()
1615 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr); in LowerDIVREM24()
1618 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb); in LowerDIVREM24()
2020 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFRINT()
2050 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff); in LowerFROUND32()
|
| D | SIISelLowering.cpp | 1463 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS); in LowerFDIV32()
1819 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X) in performAndCombine()
1968 if (CC == ISD::SETOEQ && LHS.getOpcode() == ISD::FABS) { in performSetCCCombine()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1613 setOperationAction(ISD::FABS, MVT::f64, Custom); in SparcTargetLowering()
1704 setOperationAction(ISD::FABS, MVT::f128, Legal); in SparcTargetLowering()
1707 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1726 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
2627 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
2780 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
2963 case ISD::FABS: in LowerOperation()
|
| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1065 FABS = FABS_s, enumerator
|
| D | disasm-arm64.cc | 999 FORMAT(FABS, "fabs"); in VisitFPDataProcessing1Source()
|
| /external/pcre/dist/sljit/ |
| D | sljitNativeARM_64.c | 82 #define FABS 0x1e60c000 macro
1709 FAIL_IF(push_inst(compiler, (FABS ^ inv_bits) | VD(dst_r) | VN(src))); in sljit_emit_fop1()
|
| D | sljitNativePPC_common.c | 160 #define FABS (HI(63) | LO(264)) macro
1918 FAIL_IF(push_inst(compiler, FABS | FD(dst_r) | FB(src))); in sljit_emit_fop1()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 351 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
|