| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 35 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
144 return DAG.getNode(ISD::FCEIL, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 517 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
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| D | BasicTTIImpl.h | 657 ISD = ISD::FCEIL; in getIntrinsicInstrCost()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 303 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; in mightUseCTR()
354 Opcode = ISD::FCEIL; break; in mightUseCTR()
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| D | PPCISelLowering.cpp | 138 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); in PPCTargetLowering()
197 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in PPCTargetLowering()
202 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in PPCTargetLowering()
466 setOperationAction(ISD::FCEIL, VT, Expand); in PPCTargetLowering()
514 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
573 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); in PPCTargetLowering()
784 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal); in PPCTargetLowering()
789 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 164 case ISD::FCEIL: return "fceil"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 80 case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break; in SoftenFloatResult()
1002 case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break; in ExpandFloatResult()
1852 case ISD::FCEIL: in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 317 case ISD::FCEIL: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 78 case ISD::FCEIL: in ScalarizeVectorResult()
633 case ISD::FCEIL: in SplitVectorResult()
2091 case ISD::FCEIL: in WidenVectorResult()
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| D | LegalizeDAG.cpp | 4085 case ISD::FCEIL: in ConvertNodeToLibcall()
4439 case ISD::FCEIL: in PromoteNode()
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| D | SelectionDAG.cpp | 2928 case ISD::FCEIL: { in getNode()
2989 case ISD::FCEIL: in getNode()
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| D | SelectionDAGBuilder.cpp | 4771 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; in visitIntrinsicCall()
5846 if (visitUnaryFloatCall(I, ISD::FCEIL)) in visitCall()
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| D | DAGCombiner.cpp | 1429 case ISD::FCEIL: return visitFCEIL(N); in visit()
9145 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0); in visitFCEIL()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 141 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 84 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
208 setOperationAction(ISD::FCEIL, MVT::f64, Custom); in AMDGPUTargetLowering()
345 setOperationAction(ISD::FCEIL, VT, Expand); in AMDGPUTargetLowering()
626 case ISD::FCEIL: return LowerFCEIL(Op, DAG); in LowerOperation()
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| D | SIISelLowering.cpp | 246 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in SITargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 287 setOperationAction(ISD::FCEIL, MVT::f16, Promote); in AArch64TargetLowering()
329 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand); in AArch64TargetLowering()
359 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand); in AArch64TargetLowering()
393 setOperationAction(ISD::FCEIL, Ty, Legal); in AArch64TargetLowering()
532 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand); in AArch64TargetLowering()
619 setOperationAction(ISD::FCEIL, Ty, Legal); in AArch64TargetLowering()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 849 setOperationAction(ISD::FCEIL, VT, Expand); in initActions()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 512 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); in ARMTargetLowering()
529 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand); in ARMTargetLowering()
546 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand); in ARMTargetLowering()
670 setOperationAction(ISD::FCEIL, MVT::f64, Expand); in ARMTargetLowering()
974 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in ARMTargetLowering()
988 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in ARMTargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 438 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 362 setOperationAction(ISD::FCEIL, VT, Legal); in SystemZTargetLowering()
401 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); in SystemZTargetLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1760 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC, in HexagonTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 661 setOperationAction(ISD::FCEIL, MVT::f80, Expand); in X86TargetLowering()
714 setOperationAction(ISD::FCEIL, VT, Expand); in X86TargetLowering()
960 setOperationAction(ISD::FCEIL, RoundedTy, Legal); in X86TargetLowering()
1082 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal); in X86TargetLowering()
1095 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal); in X86TargetLowering()
1459 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal); in X86TargetLowering()
1460 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal); in X86TargetLowering()
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