| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstructions.td | 110 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
113 "FNEG $dst, $src0",
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| D | R600ISelLowering.cpp | 493 DAG.getNode(ISD::FNEG, DL, VT, Cond)); in LowerSELECT_CC()
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| D | AMDILISelLowering.cpp | 539 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq); in LowerSDIV24()
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| /external/javassist/src/main/javassist/bytecode/ |
| D | Opcode.java | 102 int FNEG = 118; field
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| /external/mockito/cglib-and-asm/src/org/mockito/asm/ |
| D | Opcodes.java | 257 int FNEG = 118; // - field
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| D | Frame.java | 833 case Opcodes.FNEG: in execute()
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| /external/llvm/test/CodeGen/X86/ |
| D | vec_fneg.ll | 3 ; FNEG is defined as subtraction from -0.0.
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| D | fnabs.ll | 4 ; FNABS(x) operation -> FNEG (FABS(x)).
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 515 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 1146 if ((Opc == ISD::FABS || Opc == ISD::FNEG) && !HST->hasV5TOps()) in SelectBitOp()
1150 if (Opc != ISD::FABS && Opc != ISD::FNEG) { in SelectBitOp()
1182 if (Opc != ISD::FABS && Opc != ISD::FNEG) { in SelectBitOp()
1207 case ISD::FNEG: in SelectBitOp()
1251 if (Opc != ISD::FABS && Opc != ISD::FNEG) in SelectBitOp()
1334 case ISD::FNEG: in Select()
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| /external/mockito/cglib-and-asm/src/org/mockito/asm/tree/analysis/ |
| D | BasicInterpreter.java | 149 case FNEG: in unaryOperation()
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| D | BasicVerifier.java | 122 case FNEG: in unaryOperation()
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| D | Frame.java | 450 case Opcodes.FNEG: in execute()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 573 if (Op.getOpcode() == ISD::FNEG) return 2; in isNegatibleForFree()
635 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
1424 case ISD::FNEG: return visitFNEG(N); in visit()
7329 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || in visitBITCAST()
7343 if (N0.getOpcode() == ISD::FNEG) { in visitBITCAST()
7362 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
7846 DAG.getNode(ISD::FNEG, SL, VT, N1)); in visitFSUBForFMACombine()
7854 DAG.getNode(ISD::FNEG, SL, VT, in visitFSUBForFMACombine()
7859 if (N0.getOpcode() == ISD::FNEG && in visitFSUBForFMACombine()
7865 DAG.getNode(ISD::FNEG, SL, VT, N00), N01, in visitFSUBForFMACombine()
[all …]
|
| D | LegalizeFloatTypes.cpp | 93 case ISD::FNEG: R = SoftenFloatRes_FNEG(N, ResNo); break; in SoftenFloatResult()
786 case ISD::FNEG: in CanSkipSoftenFloatOperand()
801 case ISD::FNEG: in CanSkipSoftenFloatOperand()
1015 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break; in ExpandFloatResult()
1061 DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo), in ExpandFloatRes_FABS()
1245 Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo); in ExpandFloatRes_FNEG()
1246 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi); in ExpandFloatRes_FNEG()
1861 case ISD::FNEG: in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 300 case ISD::FNEG: in LegalizeOp()
716 case ISD::FNEG: in Expand()
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| D | SelectionDAGDumper.cpp | 157 case ISD::FNEG: return "fneg"; in getOperationName()
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| D | LegalizeDAG.cpp | 1726 TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) { in ExpandFCOPYSIGN()
1728 SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue); in ExpandFCOPYSIGN()
3337 case ISD::FNEG: in ExpandNode()
3429 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) { in ExpandNode()
3431 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1)); in ExpandNode()
4444 case ISD::FNEG: in PromoteNode()
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| /external/v8/src/ppc/ |
| D | constants-ppc.h | 283 FNEG = 40 << 1, // Floating Negate enumerator
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| D | disasm-ppc.cc | 1025 case FNEG: { in DecodeExt4()
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| /external/jacoco/org.jacoco.core.test/src/org/jacoco/core/internal/flow/ |
| D | LabelFlowAnalyzerTest.java | 210 testInsn(FNEG, true); in testInsn()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructions.td | 466 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
469 "FNEG $dst, $src0",
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1612 setOperationAction(ISD::FNEG, MVT::f64, Custom); in SparcTargetLowering()
1703 setOperationAction(ISD::FNEG, MVT::f128, Legal); in SparcTargetLowering()
1706 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1725 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
2627 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
2780 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
2964 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9); in LowerOperation()
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1068 FNEG = FNEG_s, enumerator
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| /external/javassist/src/main/javassist/bytecode/analysis/ |
| D | Executor.java | 374 case FNEG: in execute()
|