| /external/llvm/test/CodeGen/X86/ |
| D | frem-msvc32.ll | 1 ; Make sure that 32-bit FREM is promoted to 64-bit FREM on 32-bit MSVC.
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| /external/javassist/src/main/javassist/bytecode/ |
| D | Opcode.java | 103 int FREM = 114; field
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| /external/mockito/cglib-and-asm/src/org/mockito/asm/ |
| D | Opcodes.java | 253 int FREM = 114; // - field
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| D | Frame.java | 1091 case Opcodes.FREM: in execute()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 241 FADD, FSUB, FMUL, FDIV, FREM, enumerator
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| D | SelectionDAGNodes.h | 1034 case ISD::FREM:
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| /external/mockito/cglib-and-asm/src/org/mockito/asm/tree/analysis/ |
| D | BasicInterpreter.java | 251 case FREM: in binaryOperation()
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| D | BasicVerifier.java | 253 case FREM: in binaryOperation()
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| D | Frame.java | 442 case Opcodes.FREM: in execute()
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| /external/jacoco/org.jacoco.core.test/src/org/jacoco/core/internal/flow/ |
| D | LabelFlowAnalyzerTest.java | 206 testInsn(FREM, true); in testInsn()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 202 case ISD::FREM: return "frem"; in getOperationName()
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| D | SelectionDAGBuilder.h | 783 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); } in visitFRem()
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| D | LegalizeFloatTypes.cpp | 99 case ISD::FREM: R = SoftenFloatRes_FREM(N); break; in SoftenFloatResult()
1028 case ISD::FREM: ExpandFloatRes_FREM(N, Lo, Hi); break; in ExpandFloatResult()
1877 case ISD::FREM: in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 274 case ISD::FREM: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 120 case ISD::FREM: in ScalarizeVectorResult()
686 case ISD::FREM: in SplitVectorResult()
2050 case ISD::FREM: in WidenVectorResult()
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| D | SelectionDAG.cpp | 3499 case ISD::FREM: in getNode()
3772 case ISD::FREM : in getNode()
3808 case ISD::FREM: in getNode()
3848 case ISD::FREM: in getNode()
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| D | FastISel.cpp | 1565 return selectBinaryOp(I, ISD::FREM); in selectOperator()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 136 ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 885 case ISD::FREM: in canOpTrap()
1565 case FRem: return ISD::FREM; in InstructionOpcodeToISD()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 98 setOperationAction(ISD::FREM, MVT::f32, Custom); in AMDGPUTargetLowering()
99 setOperationAction(ISD::FREM, MVT::f64, Custom); in AMDGPUTargetLowering()
350 setOperationAction(ISD::FREM, VT, Expand); in AMDGPUTargetLowering()
625 case ISD::FREM: return LowerFREM(Op, DAG); in LowerOperation()
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| /external/javassist/src/main/javassist/bytecode/analysis/ |
| D | Executor.java | 360 case FREM: in execute()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 138 setOperationAction(ISD::FREM, MVT::f32, Expand); in AArch64TargetLowering()
139 setOperationAction(ISD::FREM, MVT::f64, Expand); in AArch64TargetLowering()
140 setOperationAction(ISD::FREM, MVT::f80, Expand); in AArch64TargetLowering()
158 setOperationAction(ISD::FREM, MVT::f128, Expand); in AArch64TargetLowering()
283 setOperationAction(ISD::FREM, MVT::f16, Promote); in AArch64TargetLowering()
338 setOperationAction(ISD::FREM, MVT::v4f16, Expand); in AArch64TargetLowering()
370 setOperationAction(ISD::FREM, MVT::v8f16, Expand); in AArch64TargetLowering()
542 setOperationAction(ISD::FREM, MVT::v1f64, Expand); in AArch64TargetLowering()
689 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand); in addTypeForNEON()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1619 setOperationAction(ISD::FREM , MVT::f128, Expand); in SparcTargetLowering()
1624 setOperationAction(ISD::FREM , MVT::f64, Expand); in SparcTargetLowering()
1629 setOperationAction(ISD::FREM , MVT::f32, Expand); in SparcTargetLowering()
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| /external/javassist/src/main/javassist/compiler/ |
| D | CodeGen.java | 938 '%', DREM, FREM, LREM, IREM,
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1699 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1758 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
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