| /external/valgrind/VEX/priv/ |
| D | host_amd64_defs.h | 60 ST_IN HReg hregAMD64_XMM3 ( void ) { return mkHReg(False, HRcVec128, 3, 9); } in hregAMD64_XMM3()
61 ST_IN HReg hregAMD64_XMM4 ( void ) { return mkHReg(False, HRcVec128, 4, 10); } in hregAMD64_XMM4()
62 ST_IN HReg hregAMD64_XMM5 ( void ) { return mkHReg(False, HRcVec128, 5, 11); } in hregAMD64_XMM5()
63 ST_IN HReg hregAMD64_XMM6 ( void ) { return mkHReg(False, HRcVec128, 6, 12); } in hregAMD64_XMM6()
64 ST_IN HReg hregAMD64_XMM7 ( void ) { return mkHReg(False, HRcVec128, 7, 13); } in hregAMD64_XMM7()
65 ST_IN HReg hregAMD64_XMM8 ( void ) { return mkHReg(False, HRcVec128, 8, 14); } in hregAMD64_XMM8()
66 ST_IN HReg hregAMD64_XMM9 ( void ) { return mkHReg(False, HRcVec128, 9, 15); } in hregAMD64_XMM9()
67 ST_IN HReg hregAMD64_XMM10 ( void ) { return mkHReg(False, HRcVec128, 10, 16); } in hregAMD64_XMM10()
68 ST_IN HReg hregAMD64_XMM11 ( void ) { return mkHReg(False, HRcVec128, 11, 17); } in hregAMD64_XMM11()
69 ST_IN HReg hregAMD64_XMM12 ( void ) { return mkHReg(False, HRcVec128, 12, 18); } in hregAMD64_XMM12()
[all …]
|
| D | host_x86_defs.h | 64 ST_IN HReg hregX86_XMM0 ( void ) { return mkHReg(False, HRcVec128, 0, 12); } in hregX86_XMM0()
65 ST_IN HReg hregX86_XMM1 ( void ) { return mkHReg(False, HRcVec128, 1, 13); } in hregX86_XMM1()
66 ST_IN HReg hregX86_XMM2 ( void ) { return mkHReg(False, HRcVec128, 2, 14); } in hregX86_XMM2()
67 ST_IN HReg hregX86_XMM3 ( void ) { return mkHReg(False, HRcVec128, 3, 15); } in hregX86_XMM3()
68 ST_IN HReg hregX86_XMM4 ( void ) { return mkHReg(False, HRcVec128, 4, 16); } in hregX86_XMM4()
69 ST_IN HReg hregX86_XMM5 ( void ) { return mkHReg(False, HRcVec128, 5, 17); } in hregX86_XMM5()
70 ST_IN HReg hregX86_XMM6 ( void ) { return mkHReg(False, HRcVec128, 6, 18); } in hregX86_XMM6()
71 ST_IN HReg hregX86_XMM7 ( void ) { return mkHReg(False, HRcVec128, 7, 19); } in hregX86_XMM7()
|
| D | host_arm_defs.h | 68 ST_IN HReg hregARM_Q8 ( void ) { return mkHReg(False, HRcVec128, 8, 21); } in hregARM_Q8()
69 ST_IN HReg hregARM_Q9 ( void ) { return mkHReg(False, HRcVec128, 9, 22); } in hregARM_Q9()
70 ST_IN HReg hregARM_Q10 ( void ) { return mkHReg(False, HRcVec128, 10, 23); } in hregARM_Q10()
71 ST_IN HReg hregARM_Q11 ( void ) { return mkHReg(False, HRcVec128, 11, 24); } in hregARM_Q11()
72 ST_IN HReg hregARM_Q12 ( void ) { return mkHReg(False, HRcVec128, 12, 25); } in hregARM_Q12()
79 ST_IN HReg hregARM_Q13 ( void ) { return mkHReg(False, HRcVec128, 13, 31); } in hregARM_Q13()
80 ST_IN HReg hregARM_Q14 ( void ) { return mkHReg(False, HRcVec128, 14, 32); } in hregARM_Q14()
81 ST_IN HReg hregARM_Q15 ( void ) { return mkHReg(False, HRcVec128, 15, 33); } in hregARM_Q15()
|
| D | host_generic_regs.h | 121 HRcVec128=8 /* 128-bit SIMD */ enumerator
152 vassert(rc >= HRcInt32 && rc <= HRcVec128); in hregClass()
|
| D | host_arm64_defs.h | 59 ST_IN HReg hregARM64_Q16 ( void ) { return mkHReg(False, HRcVec128, 16, 15); } in hregARM64_Q16()
60 ST_IN HReg hregARM64_Q17 ( void ) { return mkHReg(False, HRcVec128, 17, 16); } in hregARM64_Q17()
61 ST_IN HReg hregARM64_Q18 ( void ) { return mkHReg(False, HRcVec128, 18, 17); } in hregARM64_Q18()
62 ST_IN HReg hregARM64_Q19 ( void ) { return mkHReg(False, HRcVec128, 19, 18); } in hregARM64_Q19()
63 ST_IN HReg hregARM64_Q20 ( void ) { return mkHReg(False, HRcVec128, 20, 19); } in hregARM64_Q20()
|
| D | host_generic_regs.c | 55 case HRcVec128: vex_printf("HRcVec128"); break; in ppHRegClass()
79 case HRcVec128: vex_printf("%%%sV%u", maybe_v, regNN); return; in ppHReg()
|
| D | host_arm_defs.c | 167 case HRcVec128: in ppHRegARM()
2598 case HRcVec128: { in genSpill_ARM()
2653 case HRcVec128: { in genReload_ARM()
2704 vassert(hregClass(r) == HRcVec128); in qregEnc()
3795 vassert(hregClass(i->ARMin.NLdStQ.dQ) == HRcVec128); in emit_ARMInstr()
3844 regD = (hregClass(i->ARMin.NUnaryS.dst->reg) == HRcVec128) in emit_ARMInstr()
3847 regM = (hregClass(i->ARMin.NUnaryS.src->reg) == HRcVec128) in emit_ARMInstr()
3990 UInt regD = (hregClass(i->ARMin.NUnary.dst) == HRcVec128) in emit_ARMInstr()
4001 regM = (hregClass(i->ARMin.NUnary.src) == HRcVec128) in emit_ARMInstr()
4206 UInt regD = (hregClass(i->ARMin.NDual.arg1) == HRcVec128) in emit_ARMInstr()
[all …]
|
| D | host_amd64_isel.c | 203 HReg reg = mkHReg(True/*virtual reg*/, HRcVec128, 0/*enc*/, env->vreg_ctr); in newVRegV()
321 vassert(hregClass(src) == HRcVec128); in mk_vMOVsd_RR()
322 vassert(hregClass(dst) == HRcVec128); in mk_vMOVsd_RR()
2559 vassert(hregClass(r) == HRcVec128); in iselFltExpr()
2746 vassert(hregClass(r) == HRcVec128); in iselDblExpr()
3113 vassert(hregClass(r) == HRcVec128); in iselVecExpr()
3728 vassert(hregClass(*rHi) == HRcVec128); in iselDVecExpr()
3729 vassert(hregClass(*rLo) == HRcVec128); in iselDVecExpr()
4991 hreg = mkHReg(True, HRcVec128, 0, j++); in iselSB_AMD64()
4994 hreg = mkHReg(True, HRcVec128, 0, j++); in iselSB_AMD64()
[all …]
|
| D | host_generic_reg_alloc2.c | 198 case HRcVec128: case HRcFlt64: in sanity_check_spill_offset()
907 case HRcVec128: case HRcFlt64: in doRegisterAllocation()
|
| D | host_arm64_isel.c | 157 HReg reg = mkHReg(True/*virtual reg*/, HRcVec128, 0, env->vreg_ctr); in newVRegV()
2130 vassert(hregClass(r) == HRcVec128); in iselV128Expr()
3410 vassert(hregClass(*rHi) == HRcVec128); in iselV256Expr()
3411 vassert(hregClass(*rLo) == HRcVec128); in iselV256Expr()
4089 hreg = mkHReg(True, HRcVec128, 0, j++); in iselSB_ARM64()
4092 hreg = mkHReg(True, HRcVec128, 0, j++); in iselSB_ARM64()
4093 hregHI = mkHReg(True, HRcVec128, 0, j++); in iselSB_ARM64()
|
| D | host_x86_defs.c | 120 case HRcVec128: in ppHRegX86()
829 vassert(hregClass(dst) == HRcVec128); in X86Instr_SseConst()
1721 case HRcVec128: in genSpill_X86()
1746 case HRcVec128: in genReload_X86()
1857 vassert(hregClass(r) == HRcVec128); in vregEnc()
|
| D | host_x86_isel.c | 234 HReg reg = mkHReg(True/*virtual reg*/, HRcVec128, 0/*enc*/, env->vreg_ctr); in newVRegV()
301 vassert(hregClass(src) == HRcVec128); in mk_vMOVsd_RR()
302 vassert(hregClass(dst) == HRcVec128); in mk_vMOVsd_RR()
3248 vassert(hregClass(r) == HRcVec128); in iselVecExpr()
4483 case Ity_V128: hreg = mkHReg(True, HRcVec128, 0, j++); break; in iselSB_X86()
|
| D | host_arm64_defs.c | 164 case HRcVec128: in ppHRegARM64()
1335 vassert(hregClass(src) == HRcVec128); in ARM64Instr_VMov()
1336 vassert(hregClass(dst) == HRcVec128); in ARM64Instr_VMov()
2530 case HRcVec128: { in genSpill_ARM64()
2571 case HRcVec128: { in genReload_ARM64()
2614 vassert(hregClass(r) == HRcVec128); in qregEnc()
|
| D | host_ppc_defs.h | 57 mkHReg(False, HRcVec128, \
|
| D | host_amd64_defs.c | 122 case HRcVec128: in ppHRegAMD64()
1967 case HRcVec128: in genSpill_AMD64()
1989 case HRcVec128: in genReload_AMD64()
2038 vassert(hregClass(r) == HRcVec128); in vregEnc3210()
|
| D | host_ppc_defs.c | 183 case HRcVec128: in ppHRegPPC()
448 vassert(hregClass(reg) == HRcVec128); in PPCVI5s_Reg()
3013 case HRcVec128: in genSpill_PPC()
3043 case HRcVec128: in genReload_PPC()
3079 vassert(hregClass(v) == HRcVec128); in vregEnc()
5271 vassert(hregClass(i->Pin.AvSplat.src->Pvi.Reg) == HRcVec128); in emit_PPCInstr()
|
| D | host_ppc_isel.c | 359 HReg reg = mkHReg(True/*vreg*/, HRcVec128, 0/*enc*/, env->vreg_ctr); in newVRegV()
1343 vassert(hregClass(vSrc) == HRcVec128); in isNan()
4847 vassert(hregClass(r) == HRcVec128); in iselVecExpr()
6245 hregLo = mkHReg(True, HRcVec128, 0, j++); in iselSB_PPC()
|
| D | host_arm_isel.c | 177 HReg reg = mkHReg(True/*virtual reg*/, HRcVec128, 0/*enc*/, env->vreg_ctr); in newVRegV()
3795 vassert(hregClass(r) == HRcVec128); in iselNeonExpr()
6400 case Ity_V128: hreg = mkHReg(True, HRcVec128, 0, j++); break; in iselSB_ARM()
|