/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
D | AArch64AddressingModes.h | 73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument 74 switch ((Imm >> 6) & 0x7) { in getShiftType() 85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument 86 return Imm & 0x3f; in getShiftValue() 99 unsigned Imm) { in getShifterImm() argument 100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm() 110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm() 118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument 119 return Imm & 0x7; in getArithShiftValue() 123 static inline AArch64_AM::ShiftExtendType getExtendType(unsigned Imm) { in getExtendType() argument [all …]
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZTargetTransformInfo.cpp | 34 int SystemZTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { in getIntImmCost() argument 46 if (Imm == 0) in getIntImmCost() 49 if (Imm.getBitWidth() <= 64) { in getIntImmCost() 51 if (isInt<32>(Imm.getSExtValue())) in getIntImmCost() 54 if (isUInt<32>(Imm.getZExtValue())) in getIntImmCost() 57 if ((Imm.getZExtValue() & 0xffffffff) == 0) in getIntImmCost() 67 const APInt &Imm, Type *Ty) { in getIntImmCost() argument 90 if (Idx == 0 && Imm.getBitWidth() <= 64) { in getIntImmCost() 95 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost() 100 if (Idx == 1 && Imm.getBitWidth() <= 64) { in getIntImmCost() [all …]
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
D | ARMAddressingModes.h | 112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument 113 return ShOp | (Imm << 3); in getSORegOpc() 124 static inline unsigned getSOImmValImm(unsigned Imm) { in getSOImmValImm() argument 125 return Imm & 0xFF; in getSOImmValImm() 129 static inline unsigned getSOImmValRot(unsigned Imm) { in getSOImmValRot() argument 130 return (Imm >> 8) * 2; in getSOImmValRot() 137 static inline unsigned getSOImmValRotate(unsigned Imm) { in getSOImmValRotate() argument 140 if ((Imm & ~255U) == 0) return 0; in getSOImmValRotate() 143 unsigned TZ = countTrailingZeros(Imm); in getSOImmValRotate() 150 if ((rotr32(Imm, RotAmt) & ~255U) == 0) in getSOImmValRotate() [all …]
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/external/llvm/lib/Target/Mips/ |
D | MipsAnalyzeImmediate.cpp | 29 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, in GetInstSeqLsADDiu() argument 31 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsADDiu() 32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); in GetInstSeqLsADDiu() 35 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, in GetInstSeqLsORi() argument 37 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsORi() 38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); in GetInstSeqLsORi() 41 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, in GetInstSeqLsSLL() argument 43 unsigned Shamt = countTrailingZeros(Imm); in GetInstSeqLsSLL() 44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); in GetInstSeqLsSLL() 48 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize, in GetInstSeqLs() argument [all …]
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D | MipsISelDAGToDAG.h | 87 virtual bool selectVSplat(SDNode *N, APInt &Imm, 90 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const; 92 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const; 94 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const; 96 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const; 98 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const; 100 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const; 102 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const; 104 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const; 106 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const; [all …]
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D | MipsSEISelDAGToDAG.h | 81 bool selectVSplat(SDNode *N, APInt &Imm, 84 bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed, 87 bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override; 89 bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override; 91 bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override; 93 bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override; 95 bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override; 97 bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override; 99 bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override; 101 bool selectVSplatSimm5(SDValue N, SDValue &Imm) const override; [all …]
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D | MipsISelDAGToDAG.cpp | 117 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm, in selectVSplat() argument 123 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const { in selectVSplatUimm1() 128 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const { in selectVSplatUimm2() 133 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const { in selectVSplatUimm3() 138 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const { in selectVSplatUimm4() 143 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const { in selectVSplatUimm5() 148 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const { in selectVSplatUimm6() 153 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const { in selectVSplatUimm8() 158 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const { in selectVSplatSimm5() 163 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const { in selectVSplatUimmPow2() [all …]
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D | MipsAnalyzeImmediate.h | 28 const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu); 37 void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 41 void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 45 void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 48 void GetInstSeqLs(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
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D | MipsSEISelDAGToDAG.cpp | 481 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm, in selectVSplat() argument 499 Imm = SplatValue; in selectVSplat() 521 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed, in selectVSplatCommon() argument 534 Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy); in selectVSplatCommon() 544 selectVSplatUimm1(SDValue N, SDValue &Imm) const { in selectVSplatUimm1() 545 return selectVSplatCommon(N, Imm, false, 1); in selectVSplatUimm1() 549 selectVSplatUimm2(SDValue N, SDValue &Imm) const { in selectVSplatUimm2() 550 return selectVSplatCommon(N, Imm, false, 2); in selectVSplatUimm2() 554 selectVSplatUimm3(SDValue N, SDValue &Imm) const { in selectVSplatUimm3() 555 return selectVSplatCommon(N, Imm, false, 3); in selectVSplatUimm3() [all …]
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/external/llvm/lib/Target/SystemZ/Disassembler/ |
D | SystemZDisassembler.cpp | 126 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { in decodeUImmOperand() argument 127 if (!isUInt<N>(Imm)) in decodeUImmOperand() 129 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand() 134 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { in decodeSImmOperand() argument 135 if (!isUInt<N>(Imm)) in decodeSImmOperand() 137 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand() 141 static DecodeStatus decodeAccessRegOperand(MCInst &Inst, uint64_t Imm, in decodeAccessRegOperand() argument 144 return decodeUImmOperand<4>(Inst, Imm); in decodeAccessRegOperand() 147 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, in decodeU1ImmOperand() argument 149 return decodeUImmOperand<1>(Inst, Imm); in decodeU1ImmOperand() [all …]
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
D | HexagonInstPrinter.cpp | 131 int64_t Imm; in prints3_6ImmOperand() local 132 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm); in prints3_6ImmOperand() 133 Imm = SignExtend64<9>(Imm); in prints3_6ImmOperand() 135 assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO."); in prints3_6ImmOperand() 136 O << formatImm(Imm/64); in prints3_6ImmOperand() 141 int64_t Imm; in prints3_7ImmOperand() local 142 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm); in prints3_7ImmOperand() 143 Imm = SignExtend64<10>(Imm); in prints3_7ImmOperand() 145 assert(((Imm & 0x7f) == 0) && "Lower 7 bits must be ZERO."); in prints3_7ImmOperand() 146 O << formatImm(Imm/128); in prints3_7ImmOperand() [all …]
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/external/llvm/lib/Target/PowerPC/ |
D | PPCTargetTransformInfo.cpp | 38 int PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { in getIntImmCost() argument 40 return BaseT::getIntImmCost(Imm, Ty); in getIntImmCost() 48 if (Imm == 0) in getIntImmCost() 51 if (Imm.getBitWidth() <= 64) { in getIntImmCost() 52 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost() 55 if (isInt<32>(Imm.getSExtValue())) { in getIntImmCost() 57 if ((Imm.getZExtValue() & 0xFFFF) == 0) in getIntImmCost() 67 int PPCTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, in getIntImmCost() argument 70 return BaseT::getIntImmCost(IID, Idx, Imm, Ty); in getIntImmCost() 85 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue())) in getIntImmCost() [all …]
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D | PPCISelDAGToDAG.cpp | 100 inline SDValue getI32Imm(unsigned Imm, SDLoc dl) { in getI32Imm() argument 101 return CurDAG->getTargetConstant(Imm, dl, MVT::i32); in getI32Imm() 106 inline SDValue getI64Imm(uint64_t Imm, SDLoc dl) { in getI64Imm() argument 107 return CurDAG->getTargetConstant(Imm, dl, MVT::i64); in getI64Imm() 111 inline SDValue getSmallIPtrImm(unsigned Imm, SDLoc dl) { in getSmallIPtrImm() argument 113 Imm, dl, PPCLowering->getPointerTy(CurDAG->getDataLayout())); in getSmallIPtrImm() 361 static bool isIntS16Immediate(SDNode *N, short &Imm) { in isIntS16Immediate() argument 365 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); in isIntS16Immediate() 367 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); in isIntS16Immediate() 369 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); in isIntS16Immediate() [all …]
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/external/llvm/lib/Target/AMDGPU/InstPrinter/ |
D | AMDGPUInstPrinter.cpp | 83 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printDSOffset() local 84 if (Imm != 0) { in printDSOffset() 232 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) { in printImmediate32() argument 233 int32_t SImm = static_cast<int32_t>(Imm); in printImmediate32() 239 if (Imm == FloatToBits(0.0f)) in printImmediate32() 241 else if (Imm == FloatToBits(1.0f)) in printImmediate32() 243 else if (Imm == FloatToBits(-1.0f)) in printImmediate32() 245 else if (Imm == FloatToBits(0.5f)) in printImmediate32() 247 else if (Imm == FloatToBits(-0.5f)) in printImmediate32() 249 else if (Imm == FloatToBits(2.0f)) in printImmediate32() [all …]
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/external/llvm/lib/Target/X86/Utils/ |
D | X86ShuffleDecode.h | 31 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 45 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 47 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 49 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 51 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 53 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 55 void DecodePSHUFLWMask(MVT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 63 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 84 void DecodeBLENDMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 86 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm, [all …]
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D | X86ShuffleDecode.cpp | 25 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodeINSERTPSMask() argument 33 unsigned ZMask = Imm & 15; in DecodeINSERTPSMask() 34 unsigned CountD = (Imm >> 4) & 3; in DecodeINSERTPSMask() 35 unsigned CountS = (Imm >> 6) & 3; in DecodeINSERTPSMask() 96 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSLLDQMask() argument 105 if (i >= Imm) M = i - Imm + l; in DecodePSLLDQMask() 110 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSRLDQMask() argument 118 unsigned Base = i + Imm; in DecodePSRLDQMask() 125 void DecodePALIGNRMask(MVT VT, unsigned Imm, in DecodePALIGNRMask() argument 128 unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8); in DecodePALIGNRMask() [all …]
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/external/llvm/lib/Target/NVPTX/InstPrinter/ |
D | NVPTXInstPrinter.cpp | 95 int64_t Imm = MO.getImm(); in printCvtMode() local 99 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG) in printCvtMode() 103 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG) in printCvtMode() 107 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) { in printCvtMode() 145 int64_t Imm = MO.getImm(); in printCmpMode() local 149 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG) in printCmpMode() 152 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) { in printCmpMode() 219 int Imm = (int) MO.getImm(); in printLdStCode() local 221 if (Imm) in printLdStCode() 224 switch (Imm) { in printLdStCode() [all …]
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/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
D | SIMCCodeEmitter.cpp | 89 static uint32_t getIntInlineImmEncoding(IntTy Imm) { in getIntInlineImmEncoding() argument 90 if (Imm >= 0 && Imm <= 64) in getIntInlineImmEncoding() 91 return 128 + Imm; in getIntInlineImmEncoding() 93 if (Imm >= -16 && Imm <= -1) in getIntInlineImmEncoding() 94 return 192 + std::abs(Imm); in getIntInlineImmEncoding() 212 int64_t Imm = 0; in encodeInstruction() local 215 Imm = Op.getImm(); in encodeInstruction() 220 OS.write((uint8_t) ((Imm >> (8 * j)) & 0xff)); in encodeInstruction()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonAsmPrinter.cpp | 195 const MCOperand &Imm, int AlignSize) { in smallData() argument 198 if (Imm.getExpr()->evaluateAsAbsolute(Value)) { in smallData() 228 assert(Imm.isExpr() && "Expected expression and found none"); in smallData() 252 OutStreamer.EmitValue(Imm.getExpr(), AlignSize); in smallData() 271 const MCOperand &Imm = MappedInst.getOperand(1); in HexagonProcessInstruction() local 274 MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 8); in HexagonProcessInstruction() 292 MCOperand &Imm = MappedInst.getOperand(1); in HexagonProcessInstruction() local 294 MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 4); in HexagonProcessInstruction() 367 int64_t Imm; in HexagonProcessInstruction() local 369 bool Success = Expr->evaluateAsAbsolute(Imm); in HexagonProcessInstruction() [all …]
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ExpandPseudoInsts.cpp | 77 static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) { in getChunk() argument 80 return (Imm >> (ChunkIdx * 16)) & 0xFFFF; in getChunk() 85 static uint64_t replicateChunk(uint64_t Imm, unsigned FromIdx, unsigned ToIdx) { in replicateChunk() argument 90 const uint64_t Chunk = getChunk(Imm, FromIdx) << ShiftAmt; in replicateChunk() 92 Imm &= ~(0xFFFFLL << ShiftAmt); in replicateChunk() 94 return Imm | Chunk; in replicateChunk() 257 static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) { in updateImm() argument 262 Imm &= ~(Mask << (Idx * 16)); in updateImm() 265 Imm |= Mask << (Idx * 16); in updateImm() 267 return Imm; in updateImm() [all …]
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/external/llvm/lib/Target/AArch64/Disassembler/ |
D | AArch64Disassembler.cpp | 83 static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm, 86 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm, 89 static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm, 91 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm, 93 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm, 95 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm, 147 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm, 149 static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm, 152 static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm, 154 static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm, [all …]
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/external/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyMCInstLower.cpp | 84 const ConstantFP *Imm = MO.getFPImm(); in Lower() local 85 if (Imm->getType()->isFloatTy()) in Lower() 86 MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToFloat()); in Lower() 87 else if (Imm->getType()->isDoubleTy()) in Lower() 88 MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToDouble()); in Lower()
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/external/llvm/include/llvm/Analysis/ |
D | TargetTransformInfo.h | 298 bool isLegalAddImmediate(int64_t Imm) const; 304 bool isLegalICmpImmediate(int64_t Imm) const; 377 int getIntImmCost(const APInt &Imm, Type *Ty) const; 382 int getIntImmCost(unsigned Opc, unsigned Idx, const APInt &Imm, 384 int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 567 virtual bool isLegalAddImmediate(int64_t Imm) = 0; 568 virtual bool isLegalICmpImmediate(int64_t Imm) = 0; 591 virtual int getIntImmCost(const APInt &Imm, Type *Ty) = 0; 592 virtual int getIntImmCost(unsigned Opc, unsigned Idx, const APInt &Imm, 594 virtual int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, [all …]
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/external/llvm/lib/IR/ |
D | AutoUpgrade.cpp | 437 unsigned Imm; in UpgradeIntrinsicCall() local 439 Imm = 0; in UpgradeIntrinsicCall() 441 Imm = 1; in UpgradeIntrinsicCall() 443 Imm = 2; in UpgradeIntrinsicCall() 445 Imm = 3; in UpgradeIntrinsicCall() 447 Imm = 4; in UpgradeIntrinsicCall() 449 Imm = 5; in UpgradeIntrinsicCall() 451 Imm = 6; in UpgradeIntrinsicCall() 453 Imm = 7; in UpgradeIntrinsicCall() 460 Builder.getInt8(Imm)}); in UpgradeIntrinsicCall() [all …]
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/external/llvm/lib/Analysis/ |
D | TargetTransformInfo.cpp | 99 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const { in isLegalAddImmediate() 100 return TTIImpl->isLegalAddImmediate(Imm); in isLegalAddImmediate() 103 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const { in isLegalICmpImmediate() 104 return TTIImpl->isLegalICmpImmediate(Imm); in isLegalICmpImmediate() 190 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const { in getIntImmCost() argument 191 int Cost = TTIImpl->getIntImmCost(Imm, Ty); in getIntImmCost() 197 const APInt &Imm, Type *Ty) const { in getIntImmCost() argument 198 int Cost = TTIImpl->getIntImmCost(Opcode, Idx, Imm, Ty); in getIntImmCost() 204 const APInt &Imm, Type *Ty) const { in getIntImmCost() argument 205 int Cost = TTIImpl->getIntImmCost(IID, Idx, Imm, Ty); in getIntImmCost()
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