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Searched refs:IsFP (Results 1 – 13 of 13) sorted by relevance

/external/v8/src/compiler/
Dregister-allocator-verifier.cc163 constraint->type_ = sequence()->IsFP(vreg) ? kFPSlot : kSlot; in BuildConstraint()
169 if (sequence()->IsFP(vreg)) { in BuildConstraint()
189 if (sequence()->IsFP(vreg)) { in BuildConstraint()
196 constraint->type_ = sequence()->IsFP(vreg) ? kFPSlot : kSlot; in BuildConstraint()
Dinstruction.h1338 bool IsFP(int virtual_register) const { in IsFP() function
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.h101 bool IsFP) const;
DMipsSEISelLowering.cpp3209 bool IsFP) const { in emitINSERT_DF_VIDX()
3253 if (IsFP) { in emitINSERT_DF_VIDX()
3279 if (IsFP) { in emitINSERT_DF_VIDX()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h825 NodeType getExtForLoadExtType(bool IsFP, LoadExtType);
/external/llvm/lib/Bitcode/Reader/
DBitcodeReader.cpp738 bool IsFP = Ty->isFPOrFPVectorTy(); in getDecodedBinaryOpcode() local
740 if (!IsFP && !Ty->isIntOrIntVectorTy()) in getDecodedBinaryOpcode()
747 return IsFP ? Instruction::FAdd : Instruction::Add; in getDecodedBinaryOpcode()
749 return IsFP ? Instruction::FSub : Instruction::Sub; in getDecodedBinaryOpcode()
751 return IsFP ? Instruction::FMul : Instruction::Mul; in getDecodedBinaryOpcode()
753 return IsFP ? -1 : Instruction::UDiv; in getDecodedBinaryOpcode()
755 return IsFP ? Instruction::FDiv : Instruction::SDiv; in getDecodedBinaryOpcode()
757 return IsFP ? -1 : Instruction::URem; in getDecodedBinaryOpcode()
759 return IsFP ? Instruction::FRem : Instruction::SRem; in getDecodedBinaryOpcode()
761 return IsFP ? -1 : Instruction::Shl; in getDecodedBinaryOpcode()
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/external/v8/test/unittests/compiler/
Dinstruction-selector-unittest.cc96 if (sequence.IsFP(virtual_register)) { in Build()
101 EXPECT_FALSE(sequence.IsFP(virtual_register)); in Build()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp2179 static unsigned getVectorComparison(ISD::CondCode CC, bool IsFP) { in getVectorComparison() argument
2183 return IsFP ? SystemZISD::VFCMPE : SystemZISD::VICMPE; in getVectorComparison()
2187 return IsFP ? SystemZISD::VFCMPHE : static_cast<SystemZISD::NodeType>(0); in getVectorComparison()
2191 return IsFP ? SystemZISD::VFCMPH : SystemZISD::VICMPH; in getVectorComparison()
2194 return IsFP ? static_cast<SystemZISD::NodeType>(0) : SystemZISD::VICMPHL; in getVectorComparison()
2205 static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, bool IsFP, in getVectorComparisonOrInvert() argument
2207 if (unsigned Opcode = getVectorComparison(CC, IsFP)) { in getVectorComparisonOrInvert()
2212 CC = ISD::getSetCCInverse(CC, !IsFP); in getVectorComparisonOrInvert()
2213 if (unsigned Opcode = getVectorComparison(CC, IsFP)) { in getVectorComparisonOrInvert()
2253 bool IsFP = CmpOp0.getValueType().isFloatingPoint(); in lowerVectorSETCC() local
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/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1072 bool IsFP = fieldFromInstruction(insn, 26, 1); in DecodeSignedLdStInstruction() local
1075 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) in DecodeSignedLdStInstruction()
/external/v8/src/compiler/ia32/
Dinstruction-selector-ia32.cc1123 sequence()->IsFP(GetVirtualRegister(input.node())) in EmitPrepareArguments()
/external/v8/src/compiler/x87/
Dinstruction-selector-x87.cc1138 sequence()->IsFP(GetVirtualRegister(input.node())) in EmitPrepareArguments()
/external/v8/src/compiler/x64/
Dinstruction-selector-x64.cc1457 sequence()->IsFP(GetVirtualRegister(input.node())) in EmitPrepareArguments()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAG.cpp230 ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) { in getExtForLoadExtType() argument
233 return IsFP ? ISD::FP_EXTEND : ISD::ANY_EXTEND; in getExtForLoadExtType()