| /external/llvm/lib/CodeGen/ |
| D | MachineVerifier.cpp | 217 LaneBitmask LaneMask) const;
237 void verifyLiveRange(const LiveRange&, unsigned, LaneBitmask LaneMask = 0);
443 LaneBitmask LaneMask) const { in report_context()
445 if (LaneMask != 0) in report_context()
446 errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n'; in report_context()
1428 LaneBitmask LaneMask) { in verifyLiveRangeValue() argument
1436 report_context(LR, Reg, LaneMask); in verifyLiveRangeValue()
1443 report_context(LR, Reg, LaneMask); in verifyLiveRangeValue()
1451 report_context(LR, Reg, LaneMask); in verifyLiveRangeValue()
1459 report_context(LR, Reg, LaneMask); in verifyLiveRangeValue()
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| D | RegisterCoalescer.cpp | 167 LaneBitmask LaneMask, CoalescerPair &CP);
172 LaneBitmask LaneMask, const CoalescerPair &CP);
804 LaneBitmask AMask = SA.LaneMask; in removeCopyByCommutingDef()
806 LaneBitmask BMask = SB.LaneMask; in removeCopyByCommutingDef()
816 SB.LaneMask = BRest; in removeCopyByCommutingDef()
823 SB.LaneMask = Common; in removeCopyByCommutingDef()
1102 if ((SR.LaneMask & SrcMask) == 0) in eliminateUndefCopy()
1123 if ((SR.LaneMask & DstMask) == 0) in eliminateUndefCopy()
1145 if ((SR.LaneMask & UseMask) == 0) in eliminateUndefCopy()
1216 if ((S.LaneMask & Mask) == 0) in updateRegDefsUses()
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| D | LiveIntervalAnalysis.cpp | 545 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg); in shrinkToUses() local
546 if ((LaneMask & SR.LaneMask) == 0) in shrinkToUses()
758 DefinedLanesMask |= SR.LaneMask; in addKillFlags()
977 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg); in updateAllRanges() local
979 if ((S.LaneMask & LaneMask) == 0) in updateAllRanges()
981 updateRange(S, Reg, S.LaneMask); in updateAllRanges()
1001 void updateRange(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) { in updateRange() argument
1008 if (LaneMask != 0) in updateRange()
1009 dbgs() << " L" << PrintLaneMask(LaneMask); in updateRange()
1018 handleMoveUp(LR, Reg, LaneMask); in updateRange()
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| D | ScheduleDAGInstrs.cpp | 415 LaneBitmask LaneMask = I->LaneMask; in addVRegDefDeps() local
417 if ((LaneMask & KillLaneMask) == 0) { in addVRegDefDeps()
422 if ((LaneMask & DefLaneMask) != 0) { in addVRegDefDeps()
432 LaneMask &= ~KillLaneMask; in addVRegDefDeps()
434 if (LaneMask != 0) { in addVRegDefDeps()
435 I->LaneMask = LaneMask; in addVRegDefDeps()
453 LaneBitmask LaneMask = DefLaneMask; in addVRegDefDeps() local
457 if ((V2SU.LaneMask & LaneMask) == 0) in addVRegDefDeps()
476 LaneBitmask OverlapMask = V2SU.LaneMask & LaneMask; in addVRegDefDeps()
477 LaneBitmask NonOverlapMask = V2SU.LaneMask & ~LaneMask; in addVRegDefDeps()
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| D | MachineBasicBlock.cpp | 291 if (LI.LaneMask != ~0u) in print()
292 OS << ':' << PrintLaneMask(LI.LaneMask); in print()
335 void MachineBasicBlock::removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) { in removeLiveIn() argument
342 I->LaneMask &= ~LaneMask; in removeLiveIn()
343 if (I->LaneMask == 0) in removeLiveIn()
347 bool MachineBasicBlock::isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) const { in isLiveIn()
351 return I != livein_end() && (I->LaneMask & LaneMask) != 0; in isLiveIn()
365 LaneBitmask LaneMask = I->LaneMask; in sortUniqueLiveIns() local
367 LaneMask |= J->LaneMask; in sortUniqueLiveIns()
369 Out->LaneMask = LaneMask; in sortUniqueLiveIns()
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| D | VirtRegMap.cpp | 266 LaneBitmask LaneMask = 0; in addLiveInsForSubRanges() local
275 LaneMask |= SR->LaneMask; in addLiveInsForSubRanges()
277 if (LaneMask == 0) in addLiveInsForSubRanges()
280 MBB->addLiveIn(PhysReg, LaneMask); in addLiveInsForSubRanges()
341 if ((SR.LaneMask & UseMask) != 0 && SR.liveAt(BaseIndex)) in readsUndefSubreg()
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| D | LiveRangeCalc.cpp | 79 LaneBitmask Common = S.LaneMask & Mask; in calculate()
83 LaneBitmask LRest = S.LaneMask & ~Mask; in calculate()
87 S.LaneMask = LRest; in calculate()
90 assert(Common == S.LaneMask); in calculate()
120 extendToUses(S, Reg, S.LaneMask); in calculate()
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| D | LiveInterval.cpp | 914 (I->end == Pos && (ActiveMask & SR.LaneMask) == 0))) in constructMainRangeFromSubranges()
918 if ((ActiveMask & SR.LaneMask) == 0 && in constructMainRangeFromSubranges()
922 EventMask |= SR.LaneMask; in constructMainRangeFromSubranges()
927 EventMask = SR.LaneMask; in constructMainRangeFromSubranges()
931 if ((ActiveMask & SR.LaneMask) != 0 && in constructMainRangeFromSubranges()
935 EventMask |= SR.LaneMask; in constructMainRangeFromSubranges()
939 EventMask = SR.LaneMask; in constructMainRangeFromSubranges()
1068 OS << " L" << PrintLaneMask(SR.LaneMask) << ' ' << SR; in print()
1107 assert((Mask & SR.LaneMask) == 0); in verify()
1108 Mask |= SR.LaneMask; in verify()
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| D | TargetRegisterInfo.cpp | 100 Printable PrintLaneMask(LaneBitmask LaneMask) { in PrintLaneMask() argument
101 return Printable([LaneMask](raw_ostream &OS) { in PrintLaneMask()
102 OS << format("%08X", LaneMask); in PrintLaneMask()
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| D | LiveRangeEdit.cpp | 229 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg); in useIsKill() local
231 if ((S.LaneMask & LaneMask) != 0 && S.Query(Idx).isKill()) in useIsKill()
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| D | RegisterScavenging.cpp | 34 void RegScavenger::setRegUsed(unsigned Reg, LaneBitmask LaneMask) { in setRegUsed() argument
37 if (UnitMask == 0 || (LaneMask & UnitMask) != 0) in setRegUsed()
57 setRegUsed(LI.PhysReg, LI.LaneMask); in initRegState()
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| D | LiveRangeCalc.h | 132 void extendToUses(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask);
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| D | LiveRegMatrix.cpp | 81 if (S.LaneMask & Mask) { in foreachUnit()
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| D | MIRPrinter.cpp | 482 if (LI.LaneMask != ~0u) in print()
483 OS << ':' << PrintLaneMask(LI.LaneMask); in print()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAGInstrs.h | 35 LaneBitmask LaneMask; member
38 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) in VReg2SUnit()
39 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} in VReg2SUnit()
50 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, in VReg2SUnitOperIdx()
52 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {} in VReg2SUnitOperIdx()
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| D | LiveInterval.h | 599 LaneBitmask LaneMask; variable
602 SubRange(LaneBitmask LaneMask) in SubRange() argument
603 : Next(nullptr), LaneMask(LaneMask) { in SubRange()
607 SubRange(LaneBitmask LaneMask, const LiveRange &Other, in SubRange() argument
609 : LiveRange(Other, Allocator), Next(nullptr), LaneMask(LaneMask) { in SubRange()
682 LaneBitmask LaneMask) { in createSubRange() argument
683 SubRange *Range = new (Allocator) SubRange(LaneMask); in createSubRange()
691 LaneBitmask LaneMask, in createSubRangeFrom() argument
693 SubRange *Range = new (Allocator) SubRange(LaneMask, CopyFrom, Allocator); in createSubRangeFrom()
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| D | MachineBasicBlock.h | 77 LaneBitmask LaneMask;
79 RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
80 : PhysReg(PhysReg), LaneMask(LaneMask) {}
345 void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask = ~0u) {
346 LiveIns.push_back(RegisterMaskPair(PhysReg, LaneMask));
363 void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask = ~0u);
366 bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask = ~0u) const;
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| D | RegisterScavenging.h | 149 void setRegUsed(unsigned Reg, LaneBitmask LaneMask = ~0u);
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| D | LiveIntervalAnalysis.h | 443 unsigned Reg, LaneBitmask LaneMask = ~0u);
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 34 : TheDef(R), EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) { in CodeGenSubRegIndex()
45 EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) { in CodeGenSubRegIndex()
87 if (LaneMask) in computeLaneMask()
88 return LaneMask; in computeLaneMask()
91 LaneMask = ~0u; in computeLaneMask()
98 LaneMask = M; in computeLaneMask()
99 return LaneMask; in computeLaneMask()
659 LaneMask(0) { in CodeGenRegisterClass()
1179 Idx.LaneMask = 1u << Bit; in computeSubRegLaneMasks()
1182 Idx.LaneMask = 0; in computeSubRegLaneMasks()
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| D | CodeGenRegisters.h | 63 mutable unsigned LaneMask; variable
311 unsigned LaneMask; variable
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| D | RegisterInfoEmitter.cpp | 1175 OS << format(" 0x%08x, // ", Idx.LaneMask) << Idx.getName() << '\n'; in runTargetDesc()
1294 << format("0x%08x,\n ", RC.LaneMask) in runTargetDesc()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 68 const LaneBitmask LaneMask; variable
217 return LaneMask; in getLaneMask()
978 Printable PrintLaneMask(LaneBitmask LaneMask);
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| /external/llvm/lib/Target/X86/Utils/ |
| D | X86ShuffleDecode.cpp | 278 unsigned LaneMask = (Imm >> (l * NumControlBits)) & ControlBitsMask; in decodeVSHUF64x2FamilyMask() local
281 LaneMask += NumLanes; in decodeVSHUF64x2FamilyMask()
283 ShuffleMask.push_back(LaneMask * NumElementsInLane + i); in decodeVSHUF64x2FamilyMask()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 10332 SmallVector<int, 8> LaneMask; in lowerVectorShuffleByMerging128BitLanes() local
10333 LaneMask.resize(NumLanes * 2, -1); in lowerVectorShuffleByMerging128BitLanes()
10336 LaneMask[2 * i + 0] = 2*Lanes[i] + 0; in lowerVectorShuffleByMerging128BitLanes()
10337 LaneMask[2 * i + 1] = 2*Lanes[i] + 1; in lowerVectorShuffleByMerging128BitLanes()
10342 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask); in lowerVectorShuffleByMerging128BitLanes()
11398 unsigned LaneMask = 0; in BUILD_VECTORtoBlendMask() local
11404 LaneMask = !Lane1Cond << i; in BUILD_VECTORtoBlendMask()
11406 LaneMask = !Lane2Cond << i; in BUILD_VECTORtoBlendMask()
11410 MaskValue |= LaneMask; in BUILD_VECTORtoBlendMask()
11412 MaskValue |= LaneMask << NumElemsInLane; in BUILD_VECTORtoBlendMask()
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