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Searched refs:LoadLatency (Results 1 – 25 of 26) sorted by relevance

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/external/llvm/include/llvm/MC/
DMCSchedule.h171 unsigned LoadLatency; member
/external/llvm/lib/Target/PowerPC/
DPPCScheduleA2.td164 let LoadLatency = 6; // Optimistic load latency assuming bypass.
DPPCScheduleG5.td122 let LoadLatency = 3; // Optimistic load latency assuming bypass.
DPPCScheduleE500mc.td315 let LoadLatency = 5; // Optimistic load latency assuming bypass.
DPPCScheduleE5500.td375 let LoadLatency = 6; // Optimistic load latency assuming bypass.
DPPCScheduleP7.td386 let LoadLatency = 3; // Optimistic load latency assuming bypass.
DPPCScheduleP8.td395 let LoadLatency = 3; // Optimistic load latency assuming bypass.
DPPCSchedule440.td601 let LoadLatency = 5; // Optimistic load latency assuming bypass.
/external/llvm/lib/Target/Hexagon/
DHexagonScheduleV55.td165 let LoadLatency = 1;
DHexagonScheduleV4.td201 let LoadLatency = 1;
DHexagonScheduleV60.td305 let LoadLatency = 1;
/external/llvm/lib/Target/X86/
DX86ScheduleSLM.td20 let LoadLatency = 3;
DX86SchedSandyBridge.td21 let LoadLatency = 4;
DX86ScheduleBtVer2.td21 let LoadLatency = 5; // FPU latency (worse case cf Integer 3 cycle latency)
DX86Schedule.td640 let LoadLatency = 4;
DX86ScheduleAtom.td540 let LoadLatency = 3; // Expected cycles, may be overriden by OperandCycles.
DX86SchedHaswell.td20 let LoadLatency = 4;
/external/llvm/include/llvm/Target/
DTargetSchedule.td73 // Target hooks allow subtargets to associate LoadLatency and
84 int LoadLatency = -1; // Cycles for loads to access the cache.
/external/llvm/lib/Target/Mips/
DMipsScheduleP5600.td13 int LoadLatency = 4;
/external/llvm/lib/Target/AArch64/
DAArch64SchedA53.td23 let LoadLatency = 3; // Optimistic load latency assuming bypass.
DAArch64SchedCyclone.td18 let LoadLatency = 4; // Optimistic load latency.
DAArch64SchedA57.td27 let LoadLatency = 4; // Optimistic load latency
/external/llvm/lib/CodeGen/
DTargetInstrInfo.cpp1035 return SchedModel.LoadLatency; in defaultDefLatency()
/external/llvm/lib/Target/ARM/
DARMScheduleA8.td1069 let LoadLatency = 2; // Optimistic load latency assuming bypass.
DARMScheduleSwift.td44 let LoadLatency = 3;

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