| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 296 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator
687 case X86II::MRM2r: case X86II::MRM3r: in getMemoryOperandNo()
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| D | X86MCCodeEmitter.cpp | 897 case X86II::MRM2r: case X86II::MRM3r: in EmitVEXOpcodePrefix()
1402 case X86II::MRM2r: case X86II::MRM3r: in encodeInstruction()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrShiftRotate.td | 343 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
345 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt),
348 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
351 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
353 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt),
356 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
359 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
361 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt),
364 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
368 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
[all …]
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| D | X86InstrControl.td | 204 def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
212 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
283 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
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| D | X86InstrMMX.td | 471 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
474 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
477 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
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| D | X86InstrFPStack.td | 292 def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">;
385 def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RST:$op),
393 def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RST:$op),
540 def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RST:$op), "fst\t$op", IIC_FST>;
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| D | X86InstrSystem.td | 426 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
568 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
571 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
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| D | X86InstrArithmetic.td | 420 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
423 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
426 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
429 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
1205 defm ADC : ArithBinOp_RFF<0x10, 0x12, 0x14, "adc", MRM2r, MRM2m, X86adc_flag,
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| D | X86InstrSSE.td | 4111 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4114 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4117 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4158 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4161 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4164 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4205 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4208 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4211 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
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| D | X86InstrInfo.td | 2190 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2191 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2409 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
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| D | X86InstrFormats.td | 30 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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| D | X86InstrAVX512.td | 4085 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
4086 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
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| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.cpp | 108 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator
718 case X86Local::MRM2r: in emitInstructionSpecifier()
854 case X86Local::MRM2r: case X86Local::MRM3r: in emitDecodePath()
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| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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| /external/llvm/docs/TableGen/ |
| D | LangIntro.rst | 547 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1821 case X86II::MRM2r: case X86II::MRM3r: // a REGISTER r/m operand and
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