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Searched refs:MicroOpBufferSize (Results 1 – 16 of 16) sorted by relevance

/external/llvm/include/llvm/MC/
DMCSchedule.h156 unsigned MicroOpBufferSize; member
210 bool isOutOfOrder() const { return MicroOpBufferSize > 1; } in isOutOfOrder()
/external/llvm/include/llvm/CodeGen/
DTargetSchedule.h149 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; } in getMicroOpBufferSize()
/external/llvm/lib/CodeGen/
DTargetSchedule.cpp270 if (SchedModel.MicroOpBufferSize <= 1) in computeOutputLatency()
/external/llvm/lib/Target/X86/
DX86ScheduleSLM.td19 let MicroOpBufferSize = 32; // Based on the reorder buffer.
DX86SchedSandyBridge.td20 let MicroOpBufferSize = 168; // Based on the reorder buffer.
DX86Schedule.td626 // MicroOpBufferSize > 1 indicates that RAW dependencies can be
639 let MicroOpBufferSize = 32;
DX86ScheduleBtVer2.td20 let MicroOpBufferSize = 64; // Retire Control Unit
DX86ScheduleAtom.td539 let MicroOpBufferSize = 0; // In-order execution, always hide latency.
DX86SchedHaswell.td19 let MicroOpBufferSize = 192; // Based on the reorder buffer.
/external/llvm/include/llvm/Target/
DTargetSchedule.td81 int MicroOpBufferSize = -1; // Max micro-ops that can be buffered.
137 // MicroOpBufferSize, which should be the minimum size of either the
/external/llvm/lib/Target/Mips/
DMipsScheduleP5600.td12 int MicroOpBufferSize = 48; // min(48, 48, 64)
/external/llvm/lib/Target/AArch64/
DAArch64SchedA53.td20 let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
DAArch64SchedCyclone.td17 let MicroOpBufferSize = 192; // Based on the reorder buffer.
DAArch64SchedA57.td26 let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
/external/llvm/lib/Target/ARM/
DARMScheduleSwift.td43 let MicroOpBufferSize = 45; // Based on NEON renamed registers.
DARMScheduleA9.td1890 let MicroOpBufferSize = 56; // Based on available renamed registers.