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Searched refs:NVIDIA (Results 1 – 16 of 16) sorted by relevance

/external/v8/src/base/
Dcpu.h47 static const int NVIDIA = 0x4e; variable
/external/skia/
DAUTHORS28 NVIDIA <*@nvidia.com>
/external/autotest/client/deps/glbench/
DUSAGE_glbench23 # board_id: NVIDIA Corporation - Quadro FX 380/PCI/SSE2
/external/llvm/docs/
DCompileCudaWithLLVM.rst53 We assume you have installed the CUDA driver and runtime. Consult the `NVIDIA
167 32-bit ones on NVIDIA GPUs due to lack of a divide unit. Many of the 64-bit
DNVPTXUsage.rst577 an explicit address space specifier. What is address space 1? NVIDIA GPU
DCodeGenerator.rst2419 the NVIDIA NVPTX code generator for LLVM. It is contributed by NVIDIA and is
2425 the official NVIDIA toolchain.
/external/libdrm/
Dconfigure.ac244 dnl $3 - GPU name/brand. Eg. Intel, NVIDIA Tegra, ...
264 LIBDRM_ATOMICS_NOT_FOUND_MSG($NOUVEAU, nouveau, NVIDIA, nouveau)
273 LIBDRM_ATOMICS_NOT_FOUND_MSG($TEGRA, tegra, NVIDIA Tegra, tegra-experimental-api)
/external/clang/include/clang/Frontend/
DLangStandards.def150 "NVIDIA CUDA(tm)",
/external/llvm/include/llvm/ADT/
DTriple.h128 NVIDIA, enumerator
/external/v8/
DAUTHORS14 NVIDIA Corporation <*@nvidia.com>
/external/llvm/lib/Support/
DTriple.cpp148 case NVIDIA: return "nvidia"; in getVendorTypeName()
408 .Case("nvidia", Triple::NVIDIA) in parseVendor()
/external/mesa3d/docs/
DRELNOTES-4.125 NVIDIA's vertex programming extension
DRELNOTES-5.141 NVIDIA's fragment-level programming feature.
/external/jmonkeyengine/engine/src/core-effects/Common/MatDefs/Water/
DWater.frag244 // This optimization won't work on NVIDIA cards if ripples are enabled
DWater15.frag245 // This optimization won't work on NVIDIA cards if ripples are enabled
/external/vulkan-validation-layers/tests/gtest-1.7.0/include/gtest/internal/
Dgtest-port.h.orig513 // with a TR1 tuple implementation. NVIDIA's CUDA NVCC compiler