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Searched refs:OpIdx (Results 1 – 25 of 41) sorted by relevance

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/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp62 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
68 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
74 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
80 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
86 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
93 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
99 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
111 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
116 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
125 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
131 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/llvm/utils/TableGen/
DCodeEmitterGen.cpp87 unsigned OpIdx; in AddCodeToMergeInOperand() local
88 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { in AddCodeToMergeInOperand()
90 OpIdx = CGI.Operands[OpIdx].MIOperandNo; in AddCodeToMergeInOperand()
91 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && in AddCodeToMergeInOperand()
114 OpIdx = NumberedOp++; in AddCodeToMergeInOperand()
117 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); in AddCodeToMergeInOperand()
128 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); in AddCodeToMergeInOperand()
134 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; in AddCodeToMergeInOperand()
193 unsigned OpIdx; in getInstructionCase() local
194 if (!CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx)) in getInstructionCase()
[all …]
DCodeGenInstruction.cpp137 unsigned OpIdx; in getOperandNamed() local
138 if (hasOperandNamed(Name, OpIdx)) return OpIdx; in getOperandNamed()
146 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const { in hasOperandNamed()
150 OpIdx = i; in hasOperandNamed()
173 unsigned OpIdx = getOperandNamed(OpName); in ParseOperandName() local
177 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp && in ParseOperandName()
183 return std::make_pair(OpIdx, 0U); in ParseOperandName()
187 DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo; in ParseOperandName()
194 return std::make_pair(OpIdx, i); in ParseOperandName()
/external/llvm/lib/Target/AArch64/
DAArch64AddressTypePromotion.cpp209 static bool shouldSExtOperand(const Instruction *Inst, int OpIdx) { in shouldSExtOperand() argument
210 if (isa<SelectInst>(Inst) && OpIdx == 0) in shouldSExtOperand()
314 for (int OpIdx = 0, EndOpIdx = Inst->getNumOperands(); OpIdx != EndOpIdx; in propagateSignExtension() local
315 ++OpIdx) { in propagateSignExtension()
316 DEBUG(dbgs() << "Operand:\n" << *(Inst->getOperand(OpIdx)) << '\n'); in propagateSignExtension()
317 if (Inst->getOperand(OpIdx)->getType() == SExt->getType() || in propagateSignExtension()
318 !shouldSExtOperand(Inst, OpIdx)) { in propagateSignExtension()
323 Value *Opnd = Inst->getOperand(OpIdx); in propagateSignExtension()
326 Inst->setOperand(OpIdx, ConstantInt::getSigned(SExt->getType(), in propagateSignExtension()
333 Inst->setOperand(OpIdx, UndefValue::get(SExt->getType())); in propagateSignExtension()
[all …]
DAArch64PromoteConstant.cpp240 unsigned OpIdx) { in shouldConvertUse() argument
243 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2) in shouldConvertUse()
247 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) in shouldConvertUse()
251 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) in shouldConvertUse()
254 if (isa<const AllocaInst>(Instr) && OpIdx > 0) in shouldConvertUse()
258 if (isa<const LoadInst>(Instr) && OpIdx > 0) in shouldConvertUse()
262 if (isa<const StoreInst>(Instr) && OpIdx > 1) in shouldConvertUse()
266 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) in shouldConvertUse()
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp388 unsigned OpIdx = 0; in ExpandVLD() local
390 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandVLD()
391 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandVLD()
403 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
406 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
407 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
410 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
417 SrcOpIdx = OpIdx++; in ExpandVLD()
420 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
421 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
[all …]
/external/llvm/lib/CodeGen/
DMachineInstr.cpp1054 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, in findInlineAsmFlagIdx() argument
1057 assert(OpIdx < getNumOperands() && "OpIdx out of range"); in findInlineAsmFlagIdx()
1060 if (OpIdx < InlineAsm::MIOp_FirstOperand) in findInlineAsmFlagIdx()
1072 if (i + NumOps > OpIdx) { in findInlineAsmFlagIdx()
1083 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint() argument
1092 return TII->getRegClass(getDesc(), OpIdx, TRI, MF); in getRegClassConstraint()
1094 if (!getOperand(OpIdx).isReg()) in getRegClassConstraint()
1099 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
1100 OpIdx = DefIdx; in getRegClassConstraint()
1103 int FlagIdx = findInlineAsmFlagIdx(OpIdx); in getRegClassConstraint()
[all …]
DExecutionDepsFix.cpp201 bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
473 bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, in shouldBreakDependence() argument
475 unsigned reg = MI->getOperand(OpIdx).getReg(); in shouldBreakDependence()
559 unsigned OpIdx = UndefReads.back().second; in processUndefReads() local
566 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg())) in processUndefReads()
567 TII->breakPartialRegDependency(UndefMI, OpIdx, TRI); in processUndefReads()
574 OpIdx = UndefReads.back().second; in processUndefReads()
DTargetInstrInfo.cpp677 unsigned OpIdx[4][4] = { in reassociateOps() local
693 MachineOperand &OpA = Prev.getOperand(OpIdx[Row][0]); in reassociateOps()
694 MachineOperand &OpB = Root.getOperand(OpIdx[Row][1]); in reassociateOps()
695 MachineOperand &OpX = Prev.getOperand(OpIdx[Row][2]); in reassociateOps()
696 MachineOperand &OpY = Root.getOperand(OpIdx[Row][3]); in reassociateOps()
1150 for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx; in getRegSequenceInputs() local
1151 OpIdx += 2) { in getRegSequenceInputs()
1152 const MachineOperand &MOReg = MI.getOperand(OpIdx); in getRegSequenceInputs()
1153 const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1); in getRegSequenceInputs()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h947 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
957 getRegClassConstraint(unsigned OpIdx,
988 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1003 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1186 void untieRegOperand(unsigned OpIdx) {
1187 MachineOperand &MO = getOperand(OpIdx);
1189 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1220 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
DScheduleDAGInstrs.h59 int OpIdx; member
62 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {} in PhysRegSUOper()
/external/llvm/lib/MC/MCDisassembler/
DDisassembler.cpp170 for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd; in getItineraryLatency() local
171 ++OpIdx) in getItineraryLatency()
172 Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx)); in getItineraryLatency()
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
DR600MCCodeEmitter.cpp63 void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
234 void R600MCCodeEmitter::EmitSrc(const MCInst &MI, unsigned OpIdx, in EmitSrc() argument
236 const MCOperand &MO = MI.getOperand(OpIdx); in EmitSrc()
271 if ((!(isFlagSet(MI, OpIdx, MO_FLAG_ABS))) in EmitSrc()
272 && (isFlagSet(MI, OpIdx, MO_FLAG_NEG) || in EmitSrc()
281 if (isFlagSet(MI, OpIdx, MO_FLAG_ABS)) { in EmitSrc()
/external/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp61 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI() local
62 if (OpIdx > -1) { in SetFlagInNewMI()
63 uint64_t Val = OldMI->getOperand(OpIdx).getImm(); in SetFlagInNewMI()
DAMDGPUOpenCLImageTypeLoweringPass.cpp121 GetArgMD(MDNode *KernelMDNode, unsigned OpIdx) { in GetArgMD() argument
125 Res.push_back(Node->getOperand(OpIdx)); in GetArgMD()
DSIInstrInfo.h377 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
381 bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
/external/llvm/include/llvm/IR/
DInstrTypes.h1423 OperandBundleUse getOperandBundleForOperand(unsigned OpIdx) const {
1424 return operandBundleFromBundleOpInfo(getBundleOpInfoForOperand(OpIdx));
1454 bool bundleOperandHasAttr(unsigned OpIdx, Attribute::AttrKind A) const {
1455 auto &BOI = getBundleOpInfoForOperand(OpIdx);
1457 return OBU.operandHasAttr(OpIdx - BOI.Begin, A);
1614 const BundleOpInfo &getBundleOpInfoForOperand(unsigned OpIdx) const {
1616 if (BOI.Begin <= OpIdx && OpIdx < BOI.End)
/external/llvm/lib/Target/Sparc/InstPrinter/
DSparcInstPrinter.h42 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.h40 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
178 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
/external/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.h93 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
/external/llvm/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.h43 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
/external/llvm/lib/ExecutionEngine/RuntimeDyld/
DRuntimeDyldChecker.cpp254 unsigned OpIdx = OpIdxExpr.getValue(); in evalDecodeOperand() local
255 if (OpIdx >= Inst.getNumOperands()) { in evalDecodeOperand()
258 ErrMsgStream << "Invalid operand index '" << format("%i", OpIdx) in evalDecodeOperand()
267 const MCOperand &Op = Inst.getOperand(OpIdx); in evalDecodeOperand()
271 ErrMsgStream << "Operand '" << format("%i", OpIdx) << "' of instruction '" in evalDecodeOperand()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.h98 unsigned OpIdx, SDep& dep) const;
DScheduleDAGSDNodes.cpp626 unsigned OpIdx, SDep& dep) const{ in computeOperandLatency() argument
634 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency()
637 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs(); in computeOperandLatency()
638 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()

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