| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyMachineFunctionInfo.h | 87 void addPReg(unsigned PReg, unsigned WAReg) { in addPReg() argument
88 assert(PReg < WebAssembly::NUM_TARGET_REGS); in addPReg()
90 PhysRegs[PReg] = WAReg; in addPReg()
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| D | WebAssemblyAsmPrinter.cpp | 188 for (unsigned PReg = 0; PReg < PhysRegs.size(); ++PReg) { in EmitFunctionBodyStart() local
189 if (PhysRegs[PReg] == -1U) in EmitFunctionBodyStart()
191 Local.addOperand(MCOperand::createImm(getRegType(PReg).SimpleTy)); in EmitFunctionBodyStart()
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| /external/llvm/lib/CodeGen/ |
| D | RegAllocPBQP.cpp | 580 unsigned PReg = RawPRegOrder[I]; in initializeGraph() local
581 if (MRI.isReserved(PReg)) in initializeGraph()
585 if (!RegMaskOverlaps.empty() && !RegMaskOverlaps.test(PReg)) in initializeGraph()
590 for (MCRegUnitIterator Units(PReg, &TRI); Units.isValid(); ++Units) { in initializeGraph()
600 VRegAllowed.push_back(PReg); in initializeGraph()
677 unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1]; in mapPBQPToRegAlloc() local
679 << TRI.getName(PReg) << "\n"); in mapPBQPToRegAlloc()
680 assert(PReg != 0 && "Invalid preg selected."); in mapPBQPToRegAlloc()
681 VRM.assignVirt2Phys(VReg, PReg); in mapPBQPToRegAlloc()
705 unsigned PReg = MRI.getSimpleHint(LI.reg); in finalizeAlloc() local
[all …]
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| D | CallingConvLower.cpp | 245 for (MCPhysReg PReg : RemainingRegs) { in analyzeMustTailForwardedRegisters() local
246 unsigned VReg = MF.addLiveIn(PReg, RC); in analyzeMustTailForwardedRegisters()
247 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
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| D | MachineFunction.cpp | 466 unsigned MachineFunction::addLiveIn(unsigned PReg, in addLiveIn() argument
469 unsigned VReg = MRI.getLiveInVirtReg(PReg); in addLiveIn()
478 assert((VRegRC == RC || (VRegRC->contains(PReg) && in addLiveIn()
484 MRI.addLiveIn(PReg, VReg); in addLiveIn()
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| D | MachineRegisterInfo.cpp | 358 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { in getLiveInVirtReg()
360 if (I->first == PReg) in getLiveInVirtReg()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ExpandSpecialInstrs.cpp | 122 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister( in runOnMachineFunction() local
134 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); in runOnMachineFunction()
151 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister( in runOnMachineFunction() local
163 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); in runOnMachineFunction()
181 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister( in runOnMachineFunction() local
187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); in runOnMachineFunction()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBitTracker.h | 46 unsigned getNextPhysReg(unsigned PReg, unsigned Width) const;
47 unsigned getVirtRegFor(unsigned PReg) const;
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| D | HexagonBitTracker.cpp | 1129 unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const { in getNextPhysReg() argument
1131 bool Is64 = DoubleRegsRegClass.contains(PReg); in getNextPhysReg()
1132 assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg)); in getNextPhysReg()
1140 if (PReg == 0) in getNextPhysReg()
1148 if (Phys32[Idx32] == PReg) in getNextPhysReg()
1155 if (Phys64[Idx64] == PReg) in getNextPhysReg()
1168 unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const { in getVirtRegFor()
1171 if (I->first == PReg) in getVirtRegFor()
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| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 166 ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT) in ForwardedRegister()
167 : VReg(VReg), PReg(PReg), VT(VT) {} in ForwardedRegister()
169 MCPhysReg PReg; member
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| D | MachineFunction.h | 353 unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
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| D | MachineRegisterInfo.h | 740 unsigned getLiveInVirtReg(unsigned PReg) const;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 933 unsigned PReg = PMO.getReg(); in FormCandidates() local
934 unsigned PRegNum = PMO.isUndef() ? UINT_MAX : TRI->getEncodingValue(PReg); in FormCandidates()
943 PReg == getLoadStoreBaseOp(*MI).getReg()) in FormCandidates()
954 if (PReg == ARM::SP || PReg == ARM::PC) in FormCandidates()
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 2364 unsigned ScratchReg, SPReg, PReg, SPLimitOffset; in adjustForHiPEPrologue() local
2368 PReg = X86::RBP; in adjustForHiPEPrologue()
2375 PReg = X86::EBP; in adjustForHiPEPrologue()
2391 .addReg(ScratchReg), PReg, false, SPLimitOffset); in adjustForHiPEPrologue()
2400 .addReg(ScratchReg), PReg, false, SPLimitOffset); in adjustForHiPEPrologue()
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| D | X86ISelLowering.cpp | 3310 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val)); in LowerCall()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 903 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) in addLiveIn() argument
906 MF.getRegInfo().addLiveIn(PReg, VReg); in addLiveIn()
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