| /external/vulkan-validation-layers/libs/glm/detail/ |
| D | intrinsic_integer.inl | 41 __m128i Reg2; local
50 Reg2 = _mm_slli_si128(Reg1, 2);
51 Reg1 = _mm_or_si128(Reg2, Reg1);
56 Reg2 = _mm_slli_si128(Reg1, 1);
57 Reg1 = _mm_or_si128(Reg2, Reg1);
62 Reg2 = _mm_slli_epi32(Reg1, 4);
63 Reg1 = _mm_or_si128(Reg2, Reg1);
68 Reg2 = _mm_slli_epi32(Reg1, 2);
69 Reg1 = _mm_or_si128(Reg2, Reg1);
74 Reg2 = _mm_slli_epi32(Reg1, 1);
[all …]
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 378 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true); in generateCompactUnwindEncoding() local
389 Reg2 = getXRegFromWReg(Reg2); in generateCompactUnwindEncoding()
391 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
394 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
397 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
400 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
403 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
408 Reg2 = getDRegFromBReg(Reg2); in generateCompactUnwindEncoding()
414 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
417 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 739 unsigned Reg2 = CSI[idx + 1].getReg(); in spillCalleeSavedRegisters() local
761 assert(AArch64::GPR64RegClass.contains(Reg2) && in spillCalleeSavedRegisters()
769 assert(AArch64::FPR64RegClass.contains(Reg2) && in spillCalleeSavedRegisters()
779 << TRI->getName(Reg2) << ") -> fi#(" << CSI[idx].getFrameIdx() in spillCalleeSavedRegisters()
791 MBB.addLiveIn(Reg2); in spillCalleeSavedRegisters()
792 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2)) in spillCalleeSavedRegisters()
816 unsigned Reg2 = CSI[i + 1].getReg(); in restoreCalleeSavedRegisters() local
834 assert(AArch64::GPR64RegClass.contains(Reg2) && in restoreCalleeSavedRegisters()
841 assert(AArch64::FPR64RegClass.contains(Reg2) && in restoreCalleeSavedRegisters()
850 << TRI->getName(Reg2) << ") -> fi#(" << CSI[i].getFrameIdx() in restoreCalleeSavedRegisters()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.h | 73 unsigned Reg1, unsigned Reg2);
76 unsigned Reg1, unsigned Reg2, unsigned Reg3);
79 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
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| D | MipsAsmPrinter.cpp | 792 unsigned Reg2) { in EmitInstrRegReg() argument
801 Reg1 = Reg2; in EmitInstrRegReg()
802 Reg2 = Temp; in EmitInstrRegReg()
806 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegReg()
812 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
816 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegRegReg()
823 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair() argument
827 Reg1 = Reg2; in EmitMovFPIntPair()
828 Reg2 = temp; in EmitMovFPIntPair()
831 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
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| D | Mips16InstrInfo.h | 117 unsigned Reg1, unsigned Reg2) const;
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| D | Mips16InstrInfo.cpp | 265 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
276 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); in adjustStackPtrBig()
280 MIB3.addReg(Reg2, RegState::Kill); in adjustStackPtrBig()
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| D | MipsISelLowering.cpp | 2440 unsigned Reg2 = State.AllocateReg(IntRegs); in CC_MipsO32() local
2441 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) in CC_MipsO32()
3022 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), in LowerFormalArguments() local
3024 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); in LowerFormalArguments()
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | newvaluejump2.ll | 10 %Reg2 = alloca i32, align 4
11 %0 = load i32, i32* %Reg2, align 4
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 117 unsigned Reg2, bool isKill2) { in addRegReg() argument
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.h | 100 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
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| D | TargetInstrInfo.cpp | 141 unsigned Reg2 = MI->getOperand(Idx2).getReg(); in commuteInstructionImpl() local
156 Reg0 = Reg2; in commuteInstructionImpl()
158 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
176 MI->getOperand(Idx1).setReg(Reg2); in commuteInstructionImpl()
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| D | AggressiveAntiDepBreaker.cpp | 79 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) in UnionGroups() argument
86 unsigned Group2 = GetGroup(Reg2); in UnionGroups()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 662 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
665 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
667 if (Reg0 != Reg2) { in ReduceTo2Addr()
697 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
698 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
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| D | A15SDOptimizer.cpp | 89 unsigned Reg1, unsigned Reg2);
469 unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
477 .addReg(Reg2) in createRegSequence()
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| D | ARMFastISel.cpp | 2782 unsigned Reg2 = 0; in SelectShift() local
2784 Reg2 = getRegForValue(Src2Value); in SelectShift()
2785 if (Reg2 == 0) return false; in SelectShift()
2798 MIB.addReg(Reg2); in SelectShift()
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| D | ARMBaseInstrInfo.cpp | 1262 const unsigned &Reg2) -> bool { in expandMEMCPY() argument
1264 TRI.getEncodingValue(Reg2); in expandMEMCPY()
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1621 StringRef Reg2(R2); in processInstruction() local
1622 Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2))); in processInstruction()
1636 StringRef Reg2(R2); in processInstruction() local
1637 Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2))); in processInstruction()
1652 StringRef Reg2(R2); in processInstruction() local
1653 Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2))); in processInstruction()
1973 StringRef Reg2(R2); in processInstruction() local
1977 TmpInst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2))); in processInstruction()
2123 StringRef Reg2(R2); in processInstruction() local
2127 TmpInst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2))); in processInstruction()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 76 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
77 return contains(Reg1) && contains(Reg2); in contains()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 100 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
101 return MC->contains(Reg1, Reg2); in contains()
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| /external/llvm/lib/MC/ |
| D | MCDwarf.cpp | 1035 unsigned Reg2 = Instr.getRegister2(); in EmitCFIInstruction() local
1038 Reg2 = MRI->getDwarfRegNum(MRI->getLLVMRegNum(Reg2, true), false); in EmitCFIInstruction()
1042 Streamer.EmitULEB128IntValue(Reg2); in EmitCFIInstruction()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 838 unsigned Reg2 = MI->getOperand(2).getReg(); in handleSpecialSwappables() local
839 MI->getOperand(1).setReg(Reg2); in handleSpecialSwappables()
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| D | PPCInstrInfo.cpp | 350 unsigned Reg2 = MI->getOperand(2).getReg(); in commuteInstructionImpl() local
378 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); in commuteInstructionImpl()
382 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstructionImpl()
389 MI->getOperand(0).setReg(Reg2); in commuteInstructionImpl()
393 MI->getOperand(1).setReg(Reg2); in commuteInstructionImpl()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1132 CodeGenRegister *Reg2 = i1->second; in computeComposites() local
1134 if (&Reg1 == Reg2) in computeComposites()
1136 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites()
1143 if (Reg2 == Reg3) in computeComposites()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 1488 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, in emitRRR() argument
1490 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, in emitRRR()
|