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Searched refs:ResVT (Results 1 – 14 of 14) sorted by relevance

/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp4278 EVT ResVT = N->getValueType(0); in ReplaceLoadVector() local
4281 assert(ResVT.isVector() && "Vector load must have vector type"); in ReplaceLoadVector()
4286 assert(ResVT.isSimple() && "Can only handle simple types"); in ReplaceLoadVector()
4287 switch (ResVT.getSimpleVT().SimpleTy) { in ReplaceLoadVector()
4309 TD.getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext())); in ReplaceLoadVector()
4319 EVT EltVT = ResVT.getVectorElementType(); in ReplaceLoadVector()
4320 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceLoadVector()
4365 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); in ReplaceLoadVector()
4371 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes); in ReplaceLoadVector()
4394 EVT ResVT = N->getValueType(0); in ReplaceINTRINSIC_W_CHAIN() local
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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp1505 EVT ResVT = N->getValueType(0); in SplitVecOp_UnaryOp() local
1511 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_UnaryOp()
1517 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
1955 EVT ResVT = N->getValueType(0); in SplitVecOp_FP_ROUND() local
1961 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), in SplitVecOp_FP_ROUND()
1967 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in SplitVecOp_FP_ROUND()
3261 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), in WidenVecOp_SETCC() local
3265 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC, in WidenVecOp_SETCC()
DLegalizeIntegerTypes.cpp182 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_Atomic0() local
184 N->getMemoryVT(), ResVT, in PromoteIntRes_Atomic0()
DDAGCombiner.cpp10325 EVT ResVT = Use->getValueType(0); in canMergeExpensiveCrossRegisterBankCopy() local
10326 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT()); in canMergeExpensiveCrossRegisterBankCopy()
10329 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
10343 ResVT.getTypeForEVT(*DAG->getContext())); in canMergeExpensiveCrossRegisterBankCopy()
10349 if (!TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp2648 EVT ResVT = Op.getValueType(); in lowerBITCAST() local
2654 return DAG.getLoad(ResVT, DL, LoadN->getChain(), LoadN->getBasePtr(), in lowerBITCAST()
2657 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
2673 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
4538 SDValue SystemZTargetLowering::combineExtract(SDLoc DL, EVT ResVT, EVT VecVT, in combineExtract() argument
4564 return DAG.getUNDEF(ResVT); in combineExtract()
4594 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits()); in combineExtract()
4596 if (VT != ResVT) { in combineExtract()
4598 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op); in combineExtract()
4634 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp8487 EVT ResVT = N->getValueType(0); in performExtendCombine() local
8488 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT)) in performExtendCombine()
8495 if (!ResVT.isSimple() || !SrcVT.isSimple()) in performExtendCombine()
8513 unsigned NumElements = ResVT.getVectorNumElements(); in performExtendCombine()
8516 ResVT.getVectorElementType(), NumElements / 2); in performExtendCombine()
8529 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in performExtendCombine()
9510 EVT ResVT = N->getValueType(0); in performVSelectCombine() local
9514 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits()) in performVSelectCombine()
9523 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
9535 EVT ResVT = N->getValueType(0); in performSelectCombine() local
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DAArch64InstrInfo.td3753 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3756 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3760 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3773 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3775 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v2i64 V128:$Rn),
3779 def : Pat<(ResVT (AArch64dup (i32 (trunc (extractelt (v1i64 V64:$Rn),
/external/llvm/lib/Target/X86/
DX86ISelLowering.h889 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
DX86FastISel.cpp3199 EVT ResVT = VA.getValVT(); in fastLowerCall() local
3200 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in fastLowerCall()
3201 unsigned MemSize = ResVT.getSizeInBits()/8; in fastLowerCall()
3206 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; in fastLowerCall()
DX86ISelLowering.cpp4190 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, in isExtractSubvectorCheap() argument
4192 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
4195 return (Index == 0 || Index == ResVT.getVectorNumElements()); in isExtractSubvectorCheap()
6616 MVT ResVT = Op.getSimpleValueType(); in LowerAVXCONCAT_VECTORS() local
6618 assert((ResVT.is256BitVector() || in LowerAVXCONCAT_VECTORS()
6619 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide"); in LowerAVXCONCAT_VECTORS()
6623 unsigned NumElems = ResVT.getVectorNumElements(); in LowerAVXCONCAT_VECTORS()
6624 if (ResVT.is256BitVector()) in LowerAVXCONCAT_VECTORS()
6625 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl); in LowerAVXCONCAT_VECTORS()
6628 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(), in LowerAVXCONCAT_VECTORS()
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DX86InstrSSE.td7815 ValueType ResVT, ValueType OpVT, SchedWrite Sched> :
7818 [(set RC:$dst, (ResVT (X86VBroadcast (OpVT VR128:$src))))]>,
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp2365 EVT ResVT = VecVT.changeVectorElementTypeToInteger(); in SelectSETCC() local
2367 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, ResVT, LHS, RHS), 0); in SelectSETCC()
2370 ResVT, VCmp, VCmp); in SelectSETCC()
2373 return CurDAG->SelectNodeTo(N, VCmpInst, ResVT, LHS, RHS); in SelectSETCC()
DPPCISelLowering.cpp6031 EVT ResVT = Op.getValueType(); in LowerSELECT_CC() local
6048 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
6051 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6060 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
6068 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6081 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
6084 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
6091 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
6097 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
6103 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
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/external/llvm/include/llvm/Target/
DTargetLowering.h1715 virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const { in isExtractSubvectorCheap() argument