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Searched refs:SETNE (Results 1 – 25 of 46) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td20 IntRegs:$fval, SETNE)),
80 // and similarly for SETNE
83 IntRegs:$fval, SETNE)),
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp139 case ISD::SETNE: in softenSetCCOperands()
1297 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1302 Cond = ISD::SETNE; in SimplifySetCC()
1331 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
1340 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1465 case ISD::SETNE: return DAG.getConstant(1, dl, VT); in SimplifySetCC()
1482 case ISD::SETNE: in SimplifySetCC()
1505 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { in SimplifySetCC()
1514 return DAG.getConstant(Cond == ISD::SETNE, dl, VT); in SimplifySetCC()
1535 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { in SimplifySetCC()
[all …]
DLegalizeIntegerTypes.cpp554 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_SADDSUBO()
746 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_UADDSUBO()
788 ISD::SETNE); in PromoteIntRes_XMULO()
793 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE); in PromoteIntRes_XMULO()
945 case ISD::SETNE: { in PromoteSetCCOperands()
1918 DAG.getConstant(0, dl, NVT), ISD::SETNE); in ExpandIntRes_CTLZ()
1949 DAG.getConstant(0, dl, NVT), ISD::SETNE); in ExpandIntRes_CTTZ()
2194 ISD::SETEQ : ISD::SETNE); in ExpandIntRes_SADDSUBO()
2197 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); in ExpandIntRes_SADDSUBO()
2471 ISD::SETNE); in ExpandIntRes_XMULO()
[all …]
DLegalizeDAG.cpp1730 DAG.getConstant(0, DL, IntVT), ISD::SETNE); in ExpandFCOPYSIGN()
1883 case ISD::SETNE: in LegalizeSetCCCondCode()
1886 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ; in LegalizeSetCCCondCode()
2650 ISD::SETNE); in ExpandLegalINT_TO_FP()
3567 ISD::SETEQ : ISD::SETNE); in ExpandNode()
3570 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); in ExpandNode()
3673 ISD::SETNE); in ExpandNode()
3676 DAG.getConstant(0, dl, VT), ISD::SETNE); in ExpandNode()
3704 Tmp2, Tmp3, ISD::SETNE); in ExpandNode()
3757 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
[all …]
DLegalizeFloatTypes.cpp858 CCCode = ISD::SETNE; in SoftenFloatOp_BR_CC()
910 CCCode = ISD::SETNE; in SoftenFloatOp_SELECT_CC()
1555 CCCode = ISD::SETNE; in ExpandFloatOp_BR_CC()
1650 CCCode = ISD::SETNE; in ExpandFloatOp_SELECT_CC()
DSelectionDAGDumper.cpp351 case ISD::SETNE: return "setne"; in getOperationName()
/external/mesa3d/src/mesa/x86/
Dcommon_x86_asm.S66 SETNE (AL)
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h866 SETNE, // 1 X 1 1 0 True if not equal enumerator
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td42 defm NE : ComparisonInt<SETNE, "ne ">;
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp701 CCs[RTLIB::UNE_F32] = ISD::SETNE; in InitCmpLibcallCCs()
702 CCs[RTLIB::UNE_F64] = ISD::SETNE; in InitCmpLibcallCCs()
703 CCs[RTLIB::UNE_F128] = ISD::SETNE; in InitCmpLibcallCCs()
716 CCs[RTLIB::UO_F32] = ISD::SETNE; in InitCmpLibcallCCs()
717 CCs[RTLIB::UO_F64] = ISD::SETNE; in InitCmpLibcallCCs()
718 CCs[RTLIB::UO_F128] = ISD::SETNE; in InitCmpLibcallCCs()
DAnalysis.cpp188 case ISD::SETONE: case ISD::SETUNE: return ISD::SETNE; in getFCmpCodeWithoutNaN()
203 case ICmpInst::ICMP_NE: return ISD::SETNE; in getICmpCondCode()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUInstructions.td47 case ISD::SETNE: return true;}}}]
DSIISelLowering.cpp428 && CCOp == ISD::SETNE) { in PerformDAGCombine()
DR600ISelLowering.cpp455 case ISD::SETNE: in LowerSELECT_CC()
DR600Instructions.td293 0xB, "SETNE",
429 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
/external/llvm/lib/Target/AMDGPU/
DAMDGPUInstructions.td76 [{return N->get() == ISD::SETONE || N->get() == ISD::SETNE;}]
118 [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
141 [{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
DR600ISelLowering.cpp1086 DAG.getCondCode(ISD::SETNE) in LowerFPTOUINT()
1217 case ISD::SETNE: in LowerSELECT_CC()
1255 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
1983 case ISD::SETNE: return LHS; in PerformDAGCombine()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp192 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE }, in ARMTargetLowering()
193 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE }, in ARMTargetLowering()
194 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE }, in ARMTargetLowering()
195 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE }, in ARMTargetLowering()
196 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE }, in ARMTargetLowering()
197 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE }, in ARMTargetLowering()
198 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE }, in ARMTargetLowering()
202 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE }, in ARMTargetLowering()
203 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE }, in ARMTargetLowering()
204 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE }, in ARMTargetLowering()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrCMovSetCC.td101 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
DX86IntrinsicsInfo.h1685 X86_INTRINSIC_DATA(sse2_comineq_sd, COMI, X86ISD::COMI, ISD::SETNE),
1728 X86_INTRINSIC_DATA(sse2_ucomineq_sd, COMI, X86ISD::UCOMI, ISD::SETNE),
1757 X86_INTRINSIC_DATA(sse_comineq_ss, COMI, X86ISD::COMI, ISD::SETNE),
1768 X86_INTRINSIC_DATA(sse_ucomineq_ss, COMI, X86ISD::UCOMI, ISD::SETNE),
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp1995 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
2039 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
2103 case ISD::SETNE: return PPC::PRED_NE; in getPredicateForSetCC()
2139 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE in getCRIdxForSetCC()
2173 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break; in getVCmpInst()
2217 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break; in getVCmpInst()
2286 case ISD::SETNE: { in SelectSETCC()
2321 case ISD::SETNE: { in SelectSETCC()
2755 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE && in Select()
DPPCInstrInfo.td2920 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2991 defm : ExtSetCCPat<SETNE,
3100 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
3102 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
3105 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
3128 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
3168 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
3170 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3173 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3196 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
[all …]
DPPCInstrQPX.td1035 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETNE),
1082 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETNE),
1135 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETNE)),
1156 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETNE)),
1177 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETNE)),
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td1392 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1398 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1405 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1411 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp608 case ISD::SETNE: in EmitInstrWithCustomInserter()

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