| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 844 SETOEQ, // 0 0 0 1 True if ordered and equal enumerator
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstructions.td | 39 case ISD::SETOEQ: case ISD::SETUEQ:
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| D | R600ISelLowering.cpp | 448 case ISD::SETOEQ: in LowerSELECT_CC()
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 166 case FCmpInst::FCMP_OEQ: return ISD::SETOEQ; in getFCmpCondCode()
187 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrFloat.td | 54 defm EQ : ComparisonFP<SETOEQ, "eq ">;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 330 case ISD::SETOEQ: return "setoeq"; in getOperationName()
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| D | TargetLowering.cpp | 135 case ISD::SETOEQ: in softenSetCCOperands()
1830 if (Cond == ISD::SETOEQ && in SimplifySetCC()
1843 if (Cond == ISD::SETOEQ && in SimplifySetCC()
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| D | LegalizeDAG.cpp | 1845 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT) in LegalizeSetCCCondCode()
1848 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break; in LegalizeSetCCCondCode()
1854 case ISD::SETOEQ: in LegalizeSetCCCondCode()
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| D | SelectionDAG.cpp | 334 case ISD::SETOEQ: // SETEQ & SETU[LG]E in getSetCCAndOperation()
1933 case ISD::SETOEQ: in FoldSetCC()
1975 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, dl, VT); in FoldSetCC()
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| D | LegalizeFloatTypes.cpp | 1533 LHSHi, RHSHi, ISD::SETOEQ); in FloatExpandSetCCOperands()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2100 case ISD::SETOEQ: in getPredicateForSetCC()
2131 case ISD::SETOEQ: in getCRIdxForSetCC()
2174 case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break; in getVCmpInst()
2182 case ISD::SETOEQ: in getVCmpInst()
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| D | PPCInstrQPX.td | 484 (setcc v4f64:$FRA, v4f64:$FRB, SETOEQ))]>;
489 (setcc v4f32:$FRA, v4f32:$FRB, SETOEQ))]>;
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| D | PPCInstrInfo.td | 3208 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3239 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructions.td | 71 [{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
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| D | SIISelLowering.cpp | 1968 if (CC == ISD::SETOEQ && LHS.getOpcode() == ISD::FABS) { in performSetCCCombine()
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| D | AMDGPUISelLowering.cpp | 1101 case ISD::SETOEQ: in CombineFMinMaxLegacy()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 579 def SETOEQ : CondCode; def SETOGT : CondCode;
949 (setcc node:$lhs, node:$rhs, SETOEQ)>;
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 950 (setcc node:$lhs, node:$rhs, SETOEQ)>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1335 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; in FPCCToARMCC()
3762 if (CC == ISD::SETOEQ) in OptimizeVFPBrcond()
3827 (CC == ISD::SETEQ || CC == ISD::SETOEQ || in LowerBR_CC()
4632 case ISD::SETOEQ: in LowerVSETCC()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsMSAInstrInfo.td | 159 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
160 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
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| D | MipsSEISelLowering.cpp | 1802 Op->getOperand(2), ISD::SETOEQ); in lowerINTRINSIC_WO_CHAIN()
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| D | MipsISelLowering.cpp | 511 case ISD::SETOEQ: return Mips::FCOND_OEQ; in condCodeToFCC()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1870 {ISD::SETOEQ, ISD::SETOGT, ISD::SETOLT, ISD::SETOGE, ISD::SETOLE, in HexagonTargetLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1402 case ISD::SETOEQ: return SPCC::FCC_E; in FPCondCCodeToFCC()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); in X86TargetLowering()
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); in X86TargetLowering()
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); in X86TargetLowering()
4131 case ISD::SETOEQ: in TranslateX86CC()
14215 case ISD::SETOEQ: in translateX86FSETCC()
15638 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) { in LowerBRCOND()
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