| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 857 SETUNE, // 1 1 1 0 True if unordered or not equal enumerator
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstructions.td | 46 case ISD::SETONE: case ISD::SETUNE:
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| D | R600ISelLowering.cpp | 454 case ISD::SETUNE: in LowerSELECT_CC()
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 179 case FCmpInst::FCMP_UNE: return ISD::SETUNE; in getFCmpCondCode()
188 case ISD::SETONE: case ISD::SETUNE: return ISD::SETNE; in getFCmpCodeWithoutNaN()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrFloat.td | 55 defm NE : ComparisonFP<SETUNE, "ne ">;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructions.td | 108 def COND_UNE : PatLeaf <(cond), [{return N->get() == ISD::SETUNE;}]>;
118 [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
141 [{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
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| D | R600ISelLowering.cpp | 1216 case ISD::SETUNE: in LowerSELECT_CC()
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| D | SIISelLowering.cpp | 1826 if (RCC == ISD::SETUNE) { in performAndCombine()
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| D | AMDGPUISelLowering.cpp | 1103 case ISD::SETUNE: in CombineFMinMaxLegacy()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 344 case ISD::SETUNE: return "setune"; in getOperationName()
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| D | TargetLowering.cpp | 140 case ISD::SETUNE: in softenSetCCOperands()
1836 if (Cond == ISD::SETUNE && in SimplifySetCC()
1849 if (Cond == ISD::SETUNE && in SimplifySetCC()
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| D | LegalizeDAG.cpp | 1850 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT) in LegalizeSetCCCondCode()
1853 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break; in LegalizeSetCCCondCode()
1861 case ISD::SETUNE: in LegalizeSetCCCondCode()
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| D | SelectionDAG.cpp | 310 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT in getSetCCOrOperation()
1942 case ISD::SETUNE: in FoldSetCC()
2003 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, dl, VT); in FoldSetCC()
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| D | LegalizeFloatTypes.cpp | 1538 LHSHi, RHSHi, ISD::SETUNE); in FloatExpandSetCCOperands()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2102 case ISD::SETUNE: in getPredicateForSetCC()
2138 case ISD::SETUNE: in getCRIdxForSetCC()
2174 case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break; in getVCmpInst()
2218 case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break; in getVCmpInst()
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| D | PPCInstrQPX.td | 1019 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETUNE),
1066 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETUNE),
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| D | PPCInstrInfo.td | 3223 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3254 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 583 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
975 (setcc node:$lhs, node:$rhs, SETUNE)>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1353 case ISD::SETUNE: CondCode = ARMCC::NE; break; in FPCCToARMCC()
3562 if (CC == ISD::SETUNE) { in checkVSELConstraints()
3764 else if (CC == ISD::SETUNE) in OptimizeVFPBrcond()
3828 CC == ISD::SETNE || CC == ISD::SETUNE)) { in LowerBR_CC()
4630 case ISD::SETUNE: in LowerVSETCC()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 976 (setcc node:$lhs, node:$rhs, SETUNE)>;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsMSAInstrInfo.td | 185 def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
186 def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
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| D | MipsSEISelLowering.cpp | 1838 Op->getOperand(2), ISD::SETUNE); in lowerINTRINSIC_WO_CHAIN()
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| D | MipsISelLowering.cpp | 512 case ISD::SETUNE: return Mips::FCOND_UNE; in condCodeToFCC()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1855 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1404 case ISD::SETUNE: return SPCC::FCC_NE; in FPCondCCodeToFCC()
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