| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 355 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
356 assert(SubIdx && SubIdx < getNumSubRegIndices() && in getSubRegIndexName()
358 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
365 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() argument
366 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); in getSubRegIndexLaneMask()
367 return SubRegIndexLaneMasks[SubIdx]; in getSubRegIndexLaneMask()
480 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
482 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
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| D | TargetInstrInfo.h | 169 unsigned &SubIdx) const { in isCoalescableExtInstr() argument
248 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
267 unsigned DestReg, unsigned SubIdx,
355 unsigned SubIdx; member
357 unsigned SubIdx = 0)
358 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 349 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() argument
350 return SubClassWithSubReg.lookup(SubIdx); in getSubClassWithSubReg()
353 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg() argument
355 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
360 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
364 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass() argument
366 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
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| D | CodeGenRegisters.cpp | 469 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs() local
470 if (!SubIdx) in computeSecondarySubRegs()
473 NewIdx->addComposite(SI->first, SubIdx); in computeSecondarySubRegs()
899 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, in getSuperRegClasses() argument
901 auto FindI = SuperRegClasses.find(SubIdx); in getSuperRegClasses()
1554 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
1555 SubIdx != EndIdx; ++SubIdx) { in pruneUnitSets()
1556 const RegUnitSet &SubSet = RegUnitSets[SubIdx]; in pruneUnitSets()
1559 if (SuperIdx == SubIdx) in pruneUnitSets()
1568 DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx in pruneUnitSets()
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| /external/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 46 unsigned SubIdx) { in PrintReg() argument
47 return Printable([Reg, TRI, SubIdx](raw_ostream &OS) { in PrintReg()
58 if (SubIdx) { in PrintReg()
60 OS << ':' << TRI->getSubRegIndexName(SubIdx); in PrintReg()
62 OS << ":sub(" << SubIdx << ')'; in PrintReg()
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| D | ExpandPostRAPseudos.cpp | 90 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
92 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
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| D | PeepholeOptimizer.cpp | 415 unsigned SrcReg, DstReg, SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
416 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
430 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
440 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
466 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
543 .addReg(DstReg, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
546 Copy->getOperand(0).setSubReg(SubIdx); in INITIALIZE_PASS_DEPENDENCY()
1756 if (RegSeqInput.SubIdx == DefSubReg) { in getNextSourceFromRegSequence()
1798 if (InsertedReg.SubIdx == DefSubReg) { in getNextSourceFromInsertSubreg()
1817 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)) != 0) in getNextSourceFromInsertSubreg()
[all …]
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| D | MachineCopyPropagation.cpp | 120 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); in isNopCopy() local
121 if (!SubIdx) in isNopCopy()
123 return SubIdx == TRI->getSubRegIndex(SrcDef, Src); in isNopCopy()
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| D | RegisterCoalescer.cpp | 204 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
1164 unsigned SubIdx) { in updateRegDefsUses() argument
1188 if (DstInt && !Reads && SubIdx) in updateRegDefsUses()
1198 if (SubIdx && MO.isDef()) in updateRegDefsUses()
1203 if (SubIdx != 0 && MO.isUse() && MRI->shouldTrackSubRegLiveness(DstReg)) { in updateRegDefsUses()
1209 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubIdx); in updateRegDefsUses()
1238 MO.substVirtReg(DstReg, SubIdx, *TRI); in updateRegDefsUses()
1634 const unsigned SubIdx; member in __anon6ac1a90d0211::JoinVals
1789 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals() argument
1793 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask), in JoinVals()
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| D | MachineInstr.cpp | 76 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, in substVirtReg() argument
79 if (SubIdx && getSubReg()) in substVirtReg()
80 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
82 if (SubIdx) in substVirtReg()
83 setSubReg(SubIdx); in substVirtReg()
1156 if (unsigned SubIdx = MO.getSubReg()) { in getRegClassConstraintEffect() local
1158 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); in getRegClassConstraintEffect()
1160 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx); in getRegClassConstraintEffect()
1382 unsigned SubIdx, in substituteRegister() argument
1385 if (SubIdx) in substituteRegister()
[all …]
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| D | LiveDebugVariables.h | 48 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx);
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| D | TargetInstrInfo.cpp | 343 unsigned SubIdx, unsigned &Size, in getStackSlotRange() argument
346 if (!SubIdx) { in getStackSlotRange()
352 unsigned BitSize = TRI->getSubRegIdxSize(SubIdx); in getStackSlotRange()
358 int BitOffset = TRI->getSubRegIdxOffset(SubIdx); in getStackSlotRange()
376 unsigned SubIdx, in reMaterialize() argument
380 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
1182 InputReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getExtractSubregInputs()
1208 InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getInsertSubregInputs()
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| D | MachineVerifier.cpp | 915 unsigned SubIdx = MO->getSubReg(); in visitMachineOperand() local
918 if (SubIdx) { in visitMachineOperand()
933 if (SubIdx) { in visitMachineOperand()
935 TRI->getSubClassWithSubReg(RC, SubIdx); in visitMachineOperand()
939 << " does not support subreg index " << SubIdx << "\n"; in visitMachineOperand()
945 << " does not fully support subreg index " << SubIdx << "\n"; in visitMachineOperand()
951 if (SubIdx) { in visitMachineOperand()
958 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 442 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg() argument
445 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
458 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
491 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
500 SubIdx == DefSubIdx && in EmitSubregNode()
515 VReg = ConstrainForSubReg(VReg, SubIdx, in EmitSubregNode()
525 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); in EmitSubregNode()
532 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
549 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
570 MIB.addImm(SubIdx); in EmitSubregNode()
[all …]
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| D | InstrEmitter.h | 86 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
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| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
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| /external/llvm/lib/Target/ARM/ |
| D | ThumbRegisterInfo.cpp | 65 unsigned SubIdx, int Val, in emitThumb1LoadConstPool() argument
77 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
85 unsigned SubIdx, int Val, in emitThumb2LoadConstPool() argument
96 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, in emitLoadConstPool() argument
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
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| D | ThumbRegisterInfo.h | 42 DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIMachineFunctionInfo.cpp | 144 unsigned SubIdx) { in getSpilledReg() argument
150 Offset += SubIdx * 4; in getSpilledReg()
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| D | SILoadStoreOptimizer.cpp | 74 unsigned SubIdx);
198 unsigned SubIdx) { in updateRegDefsUses() argument
203 O.substVirtReg(DstReg, SubIdx, *TRI); in updateRegDefsUses()
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| D | SIRegisterInfo.h | 93 unsigned SubIdx) const;
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| D | SIMachineFunctionInfo.h | 118 unsigned SubIdx);
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 249 unsigned &SubIdx) const { in isCoalescableExtInstr()
256 SubIdx = PPC::sub_32; in isCoalescableExtInstr()
749 unsigned SubIdx; in insertSelect() local
753 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break; in insertSelect()
754 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break; in insertSelect()
755 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break; in insertSelect()
756 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break; in insertSelect()
757 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break; in insertSelect()
758 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break; in insertSelect()
759 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break; in insertSelect()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 198 unsigned &SubIdx) const override;
219 unsigned DestReg, unsigned SubIdx,
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstrInfo.h | 52 unsigned &DstReg, unsigned &SubIdx) const;
|