| /external/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 198 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
199 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef()
204 LastDefReg = SubReg; in FindLastPartialDef()
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
253 if (Processed.count(SubReg)) in HandlePhysRegUse()
255 if (PartDefRegs.count(SubReg)) in HandlePhysRegUse()
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
262 PhysRegDef[SubReg] = LastPartialDef; in HandlePhysRegUse()
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) in HandlePhysRegUse()
291 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
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| D | PeepholeOptimizer.cpp | 160 bool findNextSource(unsigned Reg, unsigned SubReg,
225 ValueTrackerResult(unsigned Reg, unsigned SubReg) : Inst(nullptr) { in ValueTrackerResult() argument
226 addSource(Reg, SubReg); in ValueTrackerResult()
257 return RegSrcs[Idx].SubReg; in getSrcSubReg()
617 bool PeepholeOptimizer::findNextSource(unsigned Reg, unsigned SubReg, in findNextSource() argument
628 TargetInstrInfo::RegSubRegPair CurSrcPair(Reg, SubReg); in findNextSource()
639 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, in findNextSource()
677 CurSrcPair.SubReg = Res.getSrcSubReg(0); in findNextSource()
686 ShouldRewrite = TRI->shouldRewriteCopySrc(DefRC, SubReg, SrcRC, in findNextSource()
687 CurSrcPair.SubReg); in findNextSource()
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| D | LiveRangeCalc.cpp | 65 unsigned SubReg = MO.getSubReg(); in calculate() local
66 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { in calculate()
67 LaneBitmask Mask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
159 unsigned SubReg = MO.getSubReg(); in extendToUses() local
160 if (SubReg != 0) { in extendToUses()
161 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
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| D | MachineInstrBundle.cpp | 187 unsigned SubReg = *SubRegs; in finalizeBundle() local
188 if (LocalDefSet.insert(SubReg).second) in finalizeBundle()
189 LocalDefs.push_back(SubReg); in finalizeBundle()
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| D | LiveIntervalAnalysis.cpp | 543 unsigned SubReg = MO.getSubReg(); in shrinkToUses() local
544 if (SubReg != 0) { in shrinkToUses()
545 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg); in shrinkToUses()
976 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
977 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg); in updateAllRanges()
1213 unsigned SubReg = MO.getSubReg(); in findLastUseBefore() local
1214 if (SubReg != 0 && LaneMask != 0 in findLastUseBefore()
1215 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0) in findLastUseBefore()
1314 unsigned SubReg = MO.getSubReg(); in repairOldRegInRange() local
1315 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in repairOldRegInRange()
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| D | VirtRegMap.cpp | 378 unsigned SubReg = MO.getSubReg(); in rewrite() local
379 if (SubReg != 0) { in rewrite()
414 PhysReg = TRI->getSubReg(PhysReg, SubReg); in rewrite()
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| D | LiveRangeEdit.cpp | 228 unsigned SubReg = MO.getSubReg(); in useIsKill() local
229 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg); in useIsKill()
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| D | TargetInstrInfo.cpp | 1181 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
1204 BaseReg.SubReg = MOBaseReg.getSubReg(); in getInsertSubregInputs()
1207 InsertedReg.SubReg = MOInsertedReg.getSubReg(); in getInsertSubregInputs()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 112 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument
114 if (SubReg) in isGPR64()
121 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument
125 SubReg == 0) || in isFPR64()
127 SubReg == AArch64::dsub); in isFPR64()
129 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
130 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
137 unsigned &SubReg) { in getSrcFromCopy() argument
138 SubReg = 0; in getSrcFromCopy()
146 SubReg = AArch64::dsub; in getSrcFromCopy()
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| D | AArch64ISelDAGToDAG.cpp | 552 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in narrowIfNeeded() local
554 dl, MVT::i32, N, SubReg); in narrowIfNeeded()
761 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in Widen() local
765 TargetOpcode::INSERT_SUBREG, dl, MVT::i64, ImpDef, N, SubReg); in Widen()
1118 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in SelectIndexedLoad() local
1123 SubReg), in SelectIndexedLoad()
1677 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in SelectBitfieldExtractOp() local
1680 SDValue(BFM, 0), SubReg); in SelectBitfieldExtractOp()
2380 unsigned SubReg; in Select() local
2388 SubReg = AArch64::dsub; in Select()
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| D | AArch64InstrInfo.cpp | 1534 int SubReg = 0, End = NumRegs, Incr = 1; in copyPhysRegTuple() local
1536 SubReg = NumRegs - 1; in copyPhysRegTuple()
1541 for (; SubReg != End; SubReg += Incr) { in copyPhysRegTuple()
1543 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); in copyPhysRegTuple()
1544 AddSubReg(MIB, SrcReg, Indices[SubReg], 0, TRI); in copyPhysRegTuple()
1545 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI); in copyPhysRegTuple()
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| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { in getSubRegIndex()
39 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
44 if (*Subs == SubReg) in getSubRegIndex()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 36 class GP8<GPR SubReg, string n> : PPCReg<n> {
37 let HWEncoding = SubReg.HWEncoding;
38 let SubRegs = [SubReg];
53 class QFPR<FPR SubReg, string n> : PPCReg<n> {
54 let HWEncoding = SubReg.HWEncoding;
55 let SubRegs = [SubReg];
67 class VR<VF SubReg, string n> : PPCReg<n> {
68 let HWEncoding{4-0} = SubReg.HWEncoding{4-0};
70 let SubRegs = [SubReg];
76 class VSRL<FPR SubReg, string n> : PPCReg<n> {
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 347 unsigned SubReg; member
348 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
349 : Reg(Reg), SubReg(SubReg) {} in Reg()
356 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
358 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
1428 std::make_pair(Val.Reg, Val.SubReg);
1434 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
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| D | TargetRegisterInfo.h | 872 unsigned SubReg, in shouldCoalesce() argument
905 unsigned SubReg; variable
916 SubReg(0),
927 unsigned getSubReg() const { return SubReg; } in getSubReg()
937 SubReg = *Idx++;
938 if (!SubReg)
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 239 unsigned SubReg = NumSubRegs > 1 ? in buildScratchLoadStore() local
244 .addReg(SubReg, getDefRegState(IsLoad)) in buildScratchLoadStore()
280 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(), in eliminateFrameIndex() local
293 .addReg(SubReg) in eliminateFrameIndex()
313 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(), in eliminateFrameIndex() local
325 SubReg) in eliminateFrameIndex()
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| D | SILowerControlFlow.cpp | 409 unsigned SubReg = TRI->getSubReg(VecReg, AMDGPU::sub0); in computeIndirectRegAndOffset() local
410 if (!SubReg) in computeIndirectRegAndOffset()
411 SubReg = VecReg; in computeIndirectRegAndOffset()
413 const TargetRegisterClass *RC = TRI->getPhysRegClass(SubReg); in computeIndirectRegAndOffset()
414 int RegIdx = TRI->getHWRegIndex(SubReg) + Offset; in computeIndirectRegAndOffset()
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| D | SIFixSGPRCopies.cpp | 200 unsigned SubReg = CopyUse.getOperand(1).getSubReg(); in foldVGPRCopyIntoRegSequence() local
201 if (SubReg != AMDGPU::NoSubRegister) in foldVGPRCopyIntoRegSequence()
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| D | R600OptimizeVectorRegisters.cpp | 192 unsigned SubReg = (*It).first; in RebuildVector() local
199 .addReg(SubReg) in RebuildVector()
201 UpdatedRegToChan[SubReg] = Chan; in RebuildVector()
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| D | SIInstrInfo.cpp | 953 unsigned SubReg = Src0.getSubReg(); in commuteInstructionImpl() local
960 Src1.setSubReg(SubReg); in commuteInstructionImpl()
1715 unsigned SubReg = MRI.createVirtualRegister(SubRC); in buildExtractSubReg() local
1718 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg) in buildExtractSubReg()
1720 return SubReg; in buildExtractSubReg()
1732 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg) in buildExtractSubReg()
1735 return SubReg; in buildExtractSubReg()
1755 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm() local
1757 return MachineOperand::CreateReg(SubReg, false); in buildExtractSubRegOrImm()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.h | 183 unsigned SubReg,
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 66 unsigned SubReg = 0) const {
76 SubReg,
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| D | MachineOperand.h | 601 unsigned SubReg = 0,
619 Op.setSubReg(SubReg);
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| /external/llvm/lib/CodeGen/MIRParser/ |
| D | MIParser.cpp | 120 bool parseSubRegisterIndex(unsigned &SubReg);
853 bool MIParser::parseSubRegisterIndex(unsigned &SubReg) { in parseSubRegisterIndex() argument
859 SubReg = getSubRegIndex(Name); in parseSubRegisterIndex()
860 if (!SubReg) in parseSubRegisterIndex()
930 unsigned SubReg = 0; in parseRegisterOperand() local
932 if (parseSubRegisterIndex(SubReg)) in parseRegisterOperand()
944 Flags & RegState::EarlyClobber, SubReg, Flags & RegState::Debug, in parseRegisterOperand()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.h | 525 bool ClearEven, unsigned SubReg) const;
|