Searched refs:SuperRC (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 608 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
611 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
619 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
621 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
715 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
716 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
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| D | RegAllocGreedy.cpp | 1550 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints() argument
1553 assert(SuperRC && "Invalid register class"); in getNumAllocatableRegsForConstraints()
1556 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, in getNumAllocatableRegsForConstraints()
1589 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
1591 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
1600 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII, in tryInstructionSplit()
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| D | TargetLoweringBase.cpp | 1168 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
1170 if (SuperRC->getSize() <= BestRC->getSize()) in findRepresentativeClass()
1172 if (!isLegalRC(SuperRC)) in findRepresentativeClass()
1174 BestRC = SuperRC; in findRepresentativeClass()
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| D | MachineVerifier.cpp | 952 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
954 if (!SuperRC) { in visitMachineOperand()
958 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 244 const TargetRegisterClass *SuperRC in mergeRead2Pair() local
246 unsigned DestReg = MRI->createVirtualRegister(SuperRC); in mergeRead2Pair()
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| D | SIInstrInfo.h | 32 const TargetRegisterClass *SuperRC,
38 const TargetRegisterClass *SuperRC,
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| D | SIInstrInfo.cpp | 1709 const TargetRegisterClass *SuperRC, in buildExtractSubReg() argument
1727 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC); in buildExtractSubReg()
1742 const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm() argument
1755 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm()
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| D | AMDGPUISelDAGToDAG.cpp | 199 const TargetRegisterClass *SuperRC = in getOperandRegClass() local
204 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, in getOperandRegClass()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 365 CodeGenRegisterClass *SuperRC) { in addSuperRegClass() argument
366 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
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