| /external/llvm/lib/CodeGen/ |
| D | IntrinsicLowering.cpp | 186 Value *Tmp3 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
192 Tmp3 = Builder.CreateAnd(Tmp3, in LowerBSWAP()
198 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or1"); in LowerBSWAP()
214 Value* Tmp3 = Builder.CreateLShr(V, in LowerBSWAP() local
239 Tmp3 = Builder.CreateAnd(Tmp3, in LowerBSWAP()
249 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or3"); in LowerBSWAP()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 602 SDValue Tmp3 = Idx; in PerformInsertVectorEltInMemory() local
612 EVT IdxVT = Tmp3.getValueType(); in PerformInsertVectorEltInMemory()
625 Tmp3 = DAG.getZExtOrTrunc(Tmp3, dl, PtrVT); in PerformInsertVectorEltInMemory()
628 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3, in PerformInsertVectorEltInMemory()
630 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); in PerformInsertVectorEltInMemory()
1776 SDValue Tmp3 = Node->getOperand(2); in ExpandDYNAMIC_STACKALLOC() local
1786 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); in ExpandDYNAMIC_STACKALLOC()
2840 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; in ExpandBSWAP() local
2849 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); in ExpandBSWAP()
2852 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, in ExpandBSWAP()
[all …]
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| D | LegalizeFloatTypes.cpp | 1531 SDValue Tmp1, Tmp2, Tmp3; in FloatExpandSetCCOperands() local
1536 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
1542 NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3); in FloatExpandSetCCOperands()
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| /external/llvm/lib/Transforms/Utils/ |
| D | IntegerDivision.cpp | 135 Value *Tmp3 = Builder.CreateXor(Tmp1, Divisor); in generateSignedDivisionCode() local
136 Value *U_Dvsr = Builder.CreateSub(Tmp3, Tmp1); in generateSignedDivisionCode()
283 Value *Tmp3 = Builder.CreateLShr(Dividend, SR_1); in generateUnsignedDivisionCode() local
351 R_1->addIncoming(Tmp3, Preheader); in generateUnsignedDivisionCode()
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| /external/webrtc/webrtc/modules/audio_coding/codecs/isac/main/source/ |
| D | structs.h | 255 double Tmp3[MAXFFTSIZE]; member
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| D | fft.c | 343 Sin = (REAL *) fftstate->Tmp3; in FFTRADIX()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2500 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
2501 bool foldedLoad = tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2504 foldedLoad = tryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2515 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), in Select()
2645 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
2646 bool foldedLoad = tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2653 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain; in Select() local
2654 if (tryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in Select()
2655 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) }; in Select()
2709 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), in Select()
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| D | X86ISelLowering.cpp | 12477 SDValue Tmp2, Tmp3; in LowerShiftParts() local
12480 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt); in LowerShiftParts()
12483 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt); in LowerShiftParts()
12496 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; in LowerShiftParts()
12497 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; in LowerShiftParts()
15763 SDValue Tmp3 = Node->getOperand(2); in LowerDYNAMIC_STACKALLOC() local
15767 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); in LowerDYNAMIC_STACKALLOC()
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| /external/clang/lib/CodeGen/ |
| D | CGExprComplex.cpp | 781 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd in EmitBinDiv() local
792 DSTr = Builder.CreateUDiv(Tmp3, Tmp6); in EmitBinDiv()
795 DSTr = Builder.CreateSDiv(Tmp3, Tmp6); in EmitBinDiv()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 2003 SDValue Tmp3 = ST->getValue(); in LowerSTOREi1() local
2004 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only"); in LowerSTOREi1()
2008 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3); in LowerSTOREi1()
2009 SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, in LowerSTOREi1()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 6657 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); in LowerSHL_PARTS() local
6658 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); in LowerSHL_PARTS()
6686 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRL_PARTS() local
6687 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRL_PARTS()
6714 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRA_PARTS() local
6715 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRA_PARTS()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1891 SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, in lowerVAARG() local
1896 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, in lowerVAARG()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4308 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); in LowerShiftLeftParts() local
4315 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc, in LowerShiftLeftParts()
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