Searched refs:UMULO (Results 1 – 13 of 13) sorted by relevance
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 196 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den); in LowerUDIVREM()
227 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den); in LowerUDIVREM()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 238 SMULO, UMULO, enumerator
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 232 case ISD::UMULO: return "umulo"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 132 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; in PromoteIntegerResult()
781 if (N->getOpcode() == ISD::UMULO) { in PromoteIntRes_XMULO()
1391 case ISD::UMULO: in ExpandIntegerResult()
2457 if (N->getOpcode() == ISD::UMULO) { in ExpandIntRes_XMULO()
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| D | SelectionDAG.cpp | 2155 case ISD::UMULO: in computeKnownBits()
2616 case ISD::UMULO: in ComputeNumSignBits()
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| D | LegalizeDAG.cpp | 3594 case ISD::UMULO: in ExpandNode()
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| D | SelectionDAGBuilder.cpp | 5085 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; in visitIntrinsicCall()
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| D | DAGCombiner.cpp | 1377 case ISD::UMULO: return visitUMULO(N); in visit()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1659 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
2866 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
2971 case ISD::UMULO: in LowerOperation()
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| /external/llvm/test/CodeGen/X86/ |
| D | xaluo.ll | 344 ; UMULO
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 262 setOperationAction(ISD::UMULO, MVT::i32, Custom); in AArch64TargetLowering()
263 setOperationAction(ISD::UMULO, MVT::i64, Custom); in AArch64TargetLowering()
1574 case ISD::UMULO: { in getAArch64XALUOOp()
2277 case ISD::UMULO: in LowerOperation()
3604 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { in LowerBR_CC()
4053 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { in LowerSELECT()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 804 setOperationAction(ISD::UMULO, VT, Expand); in initActions()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 1762 setOperationAction(ISD::UMULO, VT, Custom); in X86TargetLowering()
14992 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && in LowerSELECT()
15004 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; in LowerSELECT()
15008 if (CondOpcode == ISD::UMULO) in LowerSELECT()
15016 if (CondOpcode == ISD::UMULO) in LowerSELECT()
15475 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { in LowerBRCOND()
15528 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && in LowerBRCOND()
15553 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; in LowerBRCOND()
15559 if (CondOpcode == ISD::UMULO) in LowerBRCOND()
15567 if (CondOpcode == ISD::UMULO) in LowerBRCOND()
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