/external/llvm/lib/Target/ARM/ |
D | ARMInstrNEON.td | 275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 306 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 316 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 326 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 336 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 346 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 368 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); [all …]
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D | ARMInstrFormats.td | 1939 bits<5> Vd; 1943 let Inst{22} = Vd{4}; 1944 let Inst{15-12} = Vd{3-0}; 2009 bits<5> Vd; 2012 let Inst{15-12} = Vd{3-0}; 2013 let Inst{22} = Vd{4}; 2035 bits<5> Vd; 2038 let Inst{15-12} = Vd{3-0}; 2039 let Inst{22} = Vd{4}; 2049 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> { [all …]
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/external/v8/src/arm/ |
D | disasm-arm.cc | 90 void FormatNeonList(int Vd, int type); 399 void Decoder::FormatNeonList(int Vd, int type) { in FormatNeonList() argument 402 "{d%d}", Vd); in FormatNeonList() 405 "{d%d, d%d}", Vd, Vd + 1); in FormatNeonList() 408 "{d%d, d%d, d%d}", Vd, Vd + 1, Vd + 2); in FormatNeonList() 411 "{d%d, d%d, d%d, d%d}", Vd, Vd + 1, Vd + 2, Vd + 3); in FormatNeonList() 1776 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1); in DecodeSpecialCondition() local 1780 "vmovl.s%d q%d, d%d", imm3*8, Vd, Vm); in DecodeSpecialCondition() 1790 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1); in DecodeSpecialCondition() local 1794 "vmovl.u%d q%d, d%d", imm3*8, Vd, Vm); in DecodeSpecialCondition() [all …]
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D | simulator-arm.cc | 3824 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1); in DecodeSpecialCondition() local 3838 set_q_register(Vd, reinterpret_cast<uint64_t*>(to)); in DecodeSpecialCondition() 3848 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1); in DecodeSpecialCondition() local 3862 set_q_register(Vd, reinterpret_cast<uint64_t*>(to)); in DecodeSpecialCondition() 3870 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); in DecodeSpecialCondition() local 3896 get_d_register(Vd + r, data); in DecodeSpecialCondition() 3911 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); in DecodeSpecialCondition() local 3939 set_d_register(Vd + r, data); in DecodeSpecialCondition()
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/external/clang/include/clang/Analysis/Analyses/ |
D | ThreadSafetyTIL.h | 364 Variable(const Variable &Vd, SExpr *D) // rewrite constructor in Variable() argument 365 : SExpr(Vd), Name(Vd.Name), Definition(D), Cvdecl(Vd.Cvdecl) { in Variable() 366 Flags = Vd.kind(); in Variable() 659 Function(Variable *Vd, SExpr *Bd) in Function() argument 660 : SExpr(COP_Function), VarDecl(Vd), Body(Bd) { in Function() 661 Vd->setKind(Variable::VK_Fun); in Function() 663 Function(const Function &F, Variable *Vd, SExpr *Bd) // rewrite constructor in Function() argument 664 : SExpr(F), VarDecl(Vd), Body(Bd) { in Function() 665 Vd->setKind(Variable::VK_Fun); in Function() 710 SFunction(Variable *Vd, SExpr *B) in SFunction() argument [all …]
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/external/clang/lib/Analysis/ |
D | ThreadSafety.cpp | 243 bool containsMutexDecl(FactManager &FM, const ValueDecl* Vd) const { in containsMutexDecl() 245 return FM[ID].valueDecl() == Vd; in containsMutexDecl() 275 BeforeInfo* insertAttrExprs(const ValueDecl* Vd, 278 BeforeInfo *getBeforeInfoForDecl(const ValueDecl *Vd, 281 void checkBeforeAfter(const ValueDecl* Vd, 967 BeforeSet::BeforeInfo* BeforeSet::insertAttrExprs(const ValueDecl* Vd, in insertAttrExprs() argument 974 std::unique_ptr<BeforeInfo> &InfoPtr = BMap[Vd]; in insertAttrExprs() 980 for (Attr* At : Vd->attrs()) { in insertAttrExprs() 1008 ArgInfo->Vect.push_back(Vd); in insertAttrExprs() 1022 BeforeSet::getBeforeInfoForDecl(const ValueDecl *Vd, in getBeforeInfoForDecl() argument [all …]
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.td | 2766 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}", 2767 (NOTv8i8 V64:$Vd, V64:$Vn)>; 2768 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}", 2769 (NOTv16i8 V128:$Vd, V128:$Vn)>; 3909 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs), 3912 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2) 3915 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs), 3918 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2) 3921 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs), 3924 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2) [all …]
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D | AArch64SchedCyclone.td | 320 // FMOVv2f64ns Vd.2d, #0.0 329 // ORR.16b Vd,Vn,Vn 630 // Vd is read 5 cycles after issuing the vector load.
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D | AArch64InstrFormats.td | 5072 def : InstAlias<asm # "\t$Vd.4h, $Vn.4h, #0", 5073 (!cast<Instruction>(NAME # v4i16rz) V64:$Vd, V64:$Vn), 0>; 5074 def : InstAlias<asm # "\t$Vd.8h, $Vn.8h, #0", 5075 (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>; 5077 def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0", 5078 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>; 5079 def : InstAlias<asm # "\t$Vd.4s, $Vn.4s, #0", 5080 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>; 5081 def : InstAlias<asm # "\t$Vd.2d, $Vn.2d, #0", 5082 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>; [all …]
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/external/v8/benchmarks/ |
D | raytrace.js | 481 var Vd = this.position.dot(ray.direction); 482 if(Vd == 0) return info; // no intersection 484 var t = -(this.position.dot(ray.position) + this.d) / Vd;
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/external/valgrind/ |
D | README.aarch64 | 177 MOVs to vector registers instead of INS Vd.D[0], Xreg, to avoid false 179 the semantics of INS Vd.D[0] to see if it zeroes out the top.)
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/external/llvm/lib/Target/ARM/Disassembler/ |
D | ARMDisassembler.cpp | 1239 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeSPRRegListOperand() local 1243 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand() 1244 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeSPRRegListOperand() 1249 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeSPRRegListOperand() 1252 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeSPRRegListOperand() 1263 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeDPRRegListOperand() local 1267 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { in DecodeDPRRegListOperand() 1268 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeDPRRegListOperand() 1274 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeDPRRegListOperand() 1277 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeDPRRegListOperand() [all …]
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/external/ImageMagick/PerlMagick/t/reference/filter/ |
D | Sample.miff | 15 …�LL�@9�DE�@E�DC�B>�A<�=/�82�;/:-|:/{91|9.x9/u8.o4*v@6�TL�UMZnJUmD9C(;=34;0Vd>x�\r�\_�I\�GhaQjdSib…
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D | Crop.miff | 15 …:-|:.|:/{91{8/|9.z:.x9/u8.r6+o4*l2'v@6�TL�QM�UMyeOZnJUmDM_:9C(89,;=34;089)Vd>t�Tx�\r�\Z�C_�Ie�L\�…
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D | Magnify.miff | 15 …Vd>Vd>t�Tt�Tx�\x�\r�\r�\Z�CZ�C_�I_�Ie�Le�L\�G\�Gi`Qi`QjaRjaRlbTlbTjaRjaRjaRjaRkbSkbSkbSkbSkbSkbRlc…
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/external/doclava/res/assets/templates/assets/ |
D | prettify.js | 19 …rn d.join(P)}}var Vd=new RegExp(kc,R),Wd=/^<\!--/,Xd=/^<\[CDATA\[/,Yd=/^<br\b/i,Qa=/^<(\/?)([a-zA-…
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/external/ImageMagick/PerlMagick/t/reference/write/filter/ |
D | Sample.miff | 43 …�LL�@9�DE�@E�DC�B>�A<�=/�82�;/:-|:/{91|9.x9/u8.o4*v@6�TL�UMZnJUmD9C(;=34;0Vd>x�\r�\_�I\�GhaQjdSib…
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/external/ImageMagick/PerlMagick/t/reference/read/ |
D | input_tile.miff | 14 …Vd>t�Tx�\r�\Z�C_�Ie�L\�Gi`QjaRlbTjaRjaRkbSkbSkbRlcSlcTpbRpaUf_RfaP_YCA@%rM<�EC�BC�ON�LL�CB�@9�E;�D…
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D | input_uyvy.miff | 14 …Vd�ii��i��n›nkˉk�}o��o��n{�n{�tx�tx�no�no�py�py�x��x�Nu�Nu�Nu�Lu�Mu�Nu�Ps�Qs�Py�Oy�X��m���������…
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/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/en-GB/ |
D | en-GB_kh0_kdt_dur.pkb | 131 …�c�AWްgf��t��]a�m�sRMU�����N�jJ�h"���x_U1�"�}q!u�+tjk�Q�D�+Vd�Й$�.$�0��1K�ฅļ�0�…
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/external/ImageMagick/PerlMagick/t/reference/write/read/ |
D | input_tile.miff | 41 …Vd>t�Tx�\r�\Z�C_�Ie�L\�Gi`QjaRlbTjaRjaRkbSkbSkbRlcSlcTpbRpaUf_RfaP_YCA@%rM<�EC�BC�ON�LL�CB�@9�E;�D…
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/external/ImageMagick/PerlMagick/t/reference/write/composite/ |
D | Rotate.miff | 12 …:-|:.|:/{91{8/|9.z:.x9/u8.r6+o4*l2'v@6�TL�QM�UMyeOZnJUmDM_:9C(89,;=34;089)Vd>t�Tx�\r�\Z�C_�Ie�L\�…
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/external/ImageMagick/PerlMagick/t/bzlib/ |
D | input.miff | 9 …:-|:.|:/{91{8/|9.z:.x9/u8.r6+o4*l2'v@6�TL�QM�UMyeOZnJUmDM_:9C(89,;=34;089)Vd>t�Tx�\r�\Z�C_�Ie�L\�…
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/external/ImageMagick/PerlMagick/t/ |
D | input_p6.ppm | 4 …:-|:.|:/{91{8/|9.z:.x9/u8.r6+o4*l2'v@6�TL�QM�UMyeOZnJUmDM_:9C(89,;=34;089)Vd>t�Tx�\r�\Z�C_�Ie�L\�…
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/external/ImageMagick/PerlMagick/t/zlib/ |
D | input.miff | 9 …:-|:.|:/{91{8/|9.z:.x9/u8.r6+o4*l2'v@6�TL�QM�UMyeOZnJUmDM_:9C(89,;=34;089)Vd>t�Tx�\r�\Z�C_�Ie�L\�…
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