| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFrameLowering.cpp | 100 MRI.addLiveIn(PreloadedScratchWaveOffsetReg); in emitPrologue()
101 MBB.addLiveIn(PreloadedScratchWaveOffsetReg); in emitPrologue()
104 MRI.addLiveIn(PreloadedPrivateBufferReg); in emitPrologue()
105 MBB.addLiveIn(PreloadedPrivateBufferReg); in emitPrologue()
219 OtherBB.addLiveIn(ScratchRsrcReg); in emitPrologue()
220 OtherBB.addLiveIn(ScratchWaveOffsetReg); in emitPrologue()
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| D | SIISelLowering.cpp | 657 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass); in LowerFormalArguments()
663 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SReg_64RegClass); in LowerFormalArguments()
669 MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass); in LowerFormalArguments()
722 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass); in LowerFormalArguments()
730 Reg = MF.addLiveIn(Reg, RC); in LowerFormalArguments()
743 Reg = MF.addLiveIn(Reg, RC); in LowerFormalArguments()
766 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass); in LowerFormalArguments()
773 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass); in LowerFormalArguments()
779 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass); in LowerFormalArguments()
785 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass); in LowerFormalArguments()
[all …]
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| D | SIMachineFunctionInfo.cpp | 165 BI->addLiveIn(LaneVGPR); in getSpilledReg()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIAssignInterpRegs.cpp | 128 MRI.addLiveIn(physReg, virtReg); in AddLiveIn()
129 MF->front().addLiveIn(physReg); in AddLiveIn()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegStackify.cpp | 227 MF.getRegInfo().addLiveIn(WebAssembly::EXPR_STACK); in runOnMachineFunction()
229 MBB.addLiveIn(WebAssembly::EXPR_STACK); in runOnMachineFunction()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 149 MF.getRegInfo().addLiveIn(Mips::T9_64); in initGlobalBaseReg()
150 MBB.addLiveIn(Mips::T9_64); in initGlobalBaseReg()
177 MF.getRegInfo().addLiveIn(Mips::T9); in initGlobalBaseReg()
178 MBB.addLiveIn(Mips::T9); in initGlobalBaseReg()
212 MF.getRegInfo().addLiveIn(Mips::V0); in initGlobalBaseReg()
213 MBB.addLiveIn(Mips::V0); in initGlobalBaseReg()
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| D | MipsSEFrameLowering.cpp | 487 MBB.addLiveIn(ABI.GetEhDataReg(I)); in emitPrologue()
575 MBB.addLiveIn(Mips::COP013); in emitInterruptPrologueStub()
589 MBB.addLiveIn(Mips::COP014); in emitInterruptPrologueStub()
600 MBB.addLiveIn(Mips::COP012); in emitInterruptPrologueStub()
790 EntryBlock->addLiveIn(Reg); in spillCalleeSavedRegisters()
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| D | Mips16FrameLowering.cpp | 131 EntryBlock->addLiveIn(Reg); in spillCalleeSavedRegisters()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430FrameLowering.cpp | 78 I->addLiveIn(MSP430::FP); in emitPrologue()
200 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZFrameLowering.cpp | 121 MBB.addLiveIn(GPR64); in addSavedGPR()
205 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters()
384 I->addLiveIn(SystemZ::R11D); in emitPrologue()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcFrameLowering.cpp | 342 MBB->addLiveIn(reg - SP::I0_I1 + SP::O0_O1); in remapRegsForLeafProc()
348 MBB->addLiveIn(reg - SP::I0 + SP::O0); in remapRegsForLeafProc()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineBasicBlock.h | 345 void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask = ~0u) {
348 void addLiveIn(const RegisterMaskPair &RegMaskPair) {
360 unsigned addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC);
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| D | MachineFunction.h | 353 unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
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| /external/llvm/lib/CodeGen/ |
| D | VirtRegMap.cpp | 280 MBB->addLiveIn(PhysReg, LaneMask); in addLiveInsForSubRanges()
310 MBB->addLiveIn(PhysReg); in addMBBLiveIns()
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| D | MachineRegisterInfo.cpp | 389 EntryMBB->addLiveIn(LiveIns[i].first); in EmitLiveInCopies()
393 EntryMBB->addLiveIn(LiveIns[i].first); in EmitLiveInCopies()
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| D | CallingConvLower.cpp | 246 unsigned VReg = MF.addLiveIn(PReg, RC); in analyzeMustTailForwardedRegisters()
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| D | MachineBasicBlock.cpp | 375 MachineBasicBlock::addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC) { in addLiveIn() function in MachineBasicBlock
402 addLiveIn(PhysReg); in addLiveIn()
861 NMBB->addLiveIn(LI); in SplitCriticalEdge()
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| D | MachineFunction.cpp | 466 unsigned MachineFunction::addLiveIn(unsigned PReg, in addLiveIn() function in MachineFunction
484 MRI.addLiveIn(PReg, VReg); in addLiveIn()
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 1016 MBB.addLiveIn(Establisher); in emitPrologue()
1086 EveryMBB.addLiveIn(MachineFramePtr); in emitPrologue()
1221 MBB.addLiveIn(Establisher); in emitPrologue()
1880 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters()
1893 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters()
2085 allocMBB->addLiveIn(LI); in adjustForSegmentedStacks()
2086 checkMBB->addLiveIn(LI); in adjustForSegmentedStacks()
2090 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D); in adjustForSegmentedStacks()
2357 stackCheckMBB->addLiveIn(LI); in adjustForHiPEPrologue()
2358 incStackMBB->addLiveIn(LI); in adjustForHiPEPrologue()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCFGOptimizer.cpp | 219 LayoutSucc->addLiveIn(NewLI); in runOnMachineFunction()
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| D | HexagonISelLowering.cpp | 1073 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1078 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1086 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1093 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1101 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1108 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1114 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1422 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
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| /external/dexmaker/src/dx/java/com/android/dx/ssa/back/ |
| D | LivenessAnalyzer.java | 219 blockN.addLiveIn(regV); in liveInAtStatement()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreFrameLowering.cpp | 262 MBB.addLiveIn(XCore::LR); in emitPrologue()
287 MBB.addLiveIn(SpillList[i].Reg); in emitPrologue()
438 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 925 MBB.addLiveIn(Reg); in emitPushInst()
1143 MBB.addLiveIn(SupReg); in emitAlignedDPRCS2Spills()
1161 MBB.addLiveIn(SupReg); in emitAlignedDPRCS2Spills()
1173 MBB.addLiveIn(SupReg); in emitAlignedDPRCS2Spills()
1182 MBB.addLiveIn(NextReg); in emitAlignedDPRCS2Spills()
1898 PredBB->addLiveIn(LI); in adjustForSegmentedStacks()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 790 MBB.addLiveIn(Reg1); in spillCalleeSavedRegisters()
791 MBB.addLiveIn(Reg2); in spillCalleeSavedRegisters()
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