Searched refs:consecutive (Results 1 – 25 of 120) sorted by relevance
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/external/autotest/client/site_tests/cellular_MbimComplianceControlRequest/ |
D | control.CM05 | 8 MBIM Compliance Test: Validation for modem's responses to two consecutive 24 Validation for modem's responses to two consecutive MBIM command messages
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/external/llvm/lib/Target/ARM/ |
D | ARMRegisterInfo.td | 33 // Note: Code depends on these having consecutive numbers. 330 // These are needed by NEON instructions requiring two consecutive D registers. 336 // Register class representing a pair of consecutive D registers. 357 // Pseudo-registers representing 3 consecutive D registers. 363 // 3 consecutive D registers. 374 // (4 consecutive D registers). 388 // 4 consecutive D registers. 392 // Pseudo 512-bit registers to represent four consecutive Q registers. 396 // Pseudo 512-bit vector register class to model 4 consecutive Q registers 397 // (8 consecutive D registers). [all …]
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/external/llvm/test/MC/Mips/ |
D | micromips-invalid.s | 26 …lwm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers… 32 …swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers… 35 …lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expec… 38 …swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expec…
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/external/llvm/test/Transforms/LoopVectorize/X86/ |
D | vector_ptr_load_store.ll | 16 ; consecutive vector of pointers store, therefore we should count it towards the 43 ; However, if the store of a set of pointers is not to consecutive memory we do 93 ;; Now we check the same rules for loads. We should take consecutive loads of
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/external/deqp/doc/testspecs/GLES3/ |
D | functional.primitive_restart.txt | 32 - Use/don't use two consecutive primitive restarts 48 of the index array, or the index array contains two consecutive restarts
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/external/v8/tools/gyp/test/conditions/elseif/ |
D | elseif_bad1.gyp | 5 # Trigger an error because of two consecutive string conditions.
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D | elseif_bad2.gyp | 5 # Trigger an error because of two consecutive string conditions, even if the
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/external/llvm/test/MC/ARM/ |
D | eh-directive-vsave.s | 9 @ 0xC800: pop d[(16+x+y):(16+x)] @ d[16+x+y]-d[16+x] must be consecutive 10 @ 0xC900: pop d[(x+y):x] @ d[x+y]-d[x] must be consecutive
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/external/llvm/test/CodeGen/ARM/ |
D | MergeConsecutiveStores.ll | 3 ; Make sure that we merge the consecutive load/store sequence below and use a 34 ; Make sure that we merge the consecutive load/store sequence below and use a
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/external/llvm/lib/Fuzzer/ |
D | FuzzerFlags.def | 20 "Apply this number of consecutive mutations to each input.") 59 FUZZER_FLAG_INT(tbm_depth, 5, "Apply at most this number of consecutive"
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/external/tagsoup/ |
D | TODO | 18 Combine consecutive body elements
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/external/autotest/client/site_tests/suite_TPM/ |
D | control | 19 # 'loop=10' means run this test for 10 consecutive iterations
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/external/autotest/server/site_tests/firmware_ConsecutiveBootPowerButton/ |
D | control | 9 PURPOSE = "Servo based consecutive boot test"
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D | control.100 | 9 PURPOSE = "Servo based consecutive boot test (100 iterations)"
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D | control.dev | 9 PURPOSE = "Servo based consecutive boot test"
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D | control.dev.100 | 9 PURPOSE = "Servo based consecutive boot test"
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/external/autotest/server/site_tests/firmware_ConsecutiveBoot/ |
D | control.stress2 | 9 PURPOSE = "Servo based consecutive boot test (100 iterations)"
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D | control.stress5 | 9 PURPOSE = "Servo based consecutive boot test (100 iterations)"
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D | control.stress3 | 9 PURPOSE = "Servo based consecutive boot test (100 iterations)"
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D | control.5000 | 9 PURPOSE = "Servo based consecutive boot test (5000 iterations)"
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D | control.stress4 | 9 PURPOSE = "Servo based consecutive boot test (100 iterations)"
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D | control.500 | 9 PURPOSE = "Servo based consecutive boot test (500 iterations)"
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D | control.100 | 9 PURPOSE = "Servo based consecutive boot test (100 iterations)"
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D | control | 9 PURPOSE = "Servo based consecutive boot test"
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/external/llvm/test/CodeGen/AArch64/ |
D | postra-mi-sched.ll | 4 ; pre-RA MI scheduler, fmul, fcvt and fdiv will be consecutive. The top-down
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