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/external/autotest/client/site_tests/cellular_MbimComplianceControlRequest/
Dcontrol.CM058 MBIM Compliance Test: Validation for modem's responses to two consecutive
24 Validation for modem's responses to two consecutive MBIM command messages
/external/llvm/lib/Target/ARM/
DARMRegisterInfo.td33 // Note: Code depends on these having consecutive numbers.
330 // These are needed by NEON instructions requiring two consecutive D registers.
336 // Register class representing a pair of consecutive D registers.
357 // Pseudo-registers representing 3 consecutive D registers.
363 // 3 consecutive D registers.
374 // (4 consecutive D registers).
388 // 4 consecutive D registers.
392 // Pseudo 512-bit registers to represent four consecutive Q registers.
396 // Pseudo 512-bit vector register class to model 4 consecutive Q registers
397 // (8 consecutive D registers).
[all …]
/external/llvm/test/MC/Mips/
Dmicromips-invalid.s26 …lwm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers…
32 …swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers…
35 …lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expec…
38 …swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expec…
/external/llvm/test/Transforms/LoopVectorize/X86/
Dvector_ptr_load_store.ll16 ; consecutive vector of pointers store, therefore we should count it towards the
43 ; However, if the store of a set of pointers is not to consecutive memory we do
93 ;; Now we check the same rules for loads. We should take consecutive loads of
/external/deqp/doc/testspecs/GLES3/
Dfunctional.primitive_restart.txt32 - Use/don't use two consecutive primitive restarts
48 of the index array, or the index array contains two consecutive restarts
/external/v8/tools/gyp/test/conditions/elseif/
Delseif_bad1.gyp5 # Trigger an error because of two consecutive string conditions.
Delseif_bad2.gyp5 # Trigger an error because of two consecutive string conditions, even if the
/external/llvm/test/MC/ARM/
Deh-directive-vsave.s9 @ 0xC800: pop d[(16+x+y):(16+x)] @ d[16+x+y]-d[16+x] must be consecutive
10 @ 0xC900: pop d[(x+y):x] @ d[x+y]-d[x] must be consecutive
/external/llvm/test/CodeGen/ARM/
DMergeConsecutiveStores.ll3 ; Make sure that we merge the consecutive load/store sequence below and use a
34 ; Make sure that we merge the consecutive load/store sequence below and use a
/external/llvm/lib/Fuzzer/
DFuzzerFlags.def20 "Apply this number of consecutive mutations to each input.")
59 FUZZER_FLAG_INT(tbm_depth, 5, "Apply at most this number of consecutive"
/external/tagsoup/
DTODO18 Combine consecutive body elements
/external/autotest/client/site_tests/suite_TPM/
Dcontrol19 # 'loop=10' means run this test for 10 consecutive iterations
/external/autotest/server/site_tests/firmware_ConsecutiveBootPowerButton/
Dcontrol9 PURPOSE = "Servo based consecutive boot test"
Dcontrol.1009 PURPOSE = "Servo based consecutive boot test (100 iterations)"
Dcontrol.dev9 PURPOSE = "Servo based consecutive boot test"
Dcontrol.dev.1009 PURPOSE = "Servo based consecutive boot test"
/external/autotest/server/site_tests/firmware_ConsecutiveBoot/
Dcontrol.stress29 PURPOSE = "Servo based consecutive boot test (100 iterations)"
Dcontrol.stress59 PURPOSE = "Servo based consecutive boot test (100 iterations)"
Dcontrol.stress39 PURPOSE = "Servo based consecutive boot test (100 iterations)"
Dcontrol.50009 PURPOSE = "Servo based consecutive boot test (5000 iterations)"
Dcontrol.stress49 PURPOSE = "Servo based consecutive boot test (100 iterations)"
Dcontrol.5009 PURPOSE = "Servo based consecutive boot test (500 iterations)"
Dcontrol.1009 PURPOSE = "Servo based consecutive boot test (100 iterations)"
Dcontrol9 PURPOSE = "Servo based consecutive boot test"
/external/llvm/test/CodeGen/AArch64/
Dpostra-mi-sched.ll4 ; pre-RA MI scheduler, fmul, fcvt and fdiv will be consecutive. The top-down

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