| /external/libhevc/common/arm/ |
| D | ihevc_intra_pred_luma_planar.s | 150 vdup.s8 d5, r8 @row + 1
152 …vmov d7, d5 @mov #1 to d7 to used for inc for row+1 and dec for nt-1-r…
188 vmlal.u8 q6, d5, d0 @(1)(row+1) * src[nt-1]
200 vadd.s8 d5, d5, d7 @(1)
205 vmlal.u8 q15, d5, d0 @(2)
215 vadd.s8 d5, d5, d7 @(2)
219 vmlal.u8 q14, d5, d0 @(3)
232 vadd.s8 d5, d5, d7 @(3)
236 vmlal.u8 q5, d5, d0 @(4)
249 vadd.s8 d5, d5, d7 @(4)
[all …]
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| D | ihevc_itrans_recon_16x16.s | 230 vld1.16 d5,[r9],r6
285 vmlal.s16 q6,d5,d1[2]
287 vmlsl.s16 q7,d5,d3[2]
289 vmlsl.s16 q8,d5,d0[2]
291 vmlsl.s16 q9,d5,d2[2]
310 vld1.16 d5,[r9],r6
347 vmlal.s16 q6,d5,d3[2]
355 vmlsl.s16 q7,d5,d2[2]
361 vmlal.s16 q8,d5,d1[2]
367 vmlsl.s16 q9,d5,d0[2]
[all …]
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| D | ihevc_padding.s | 138 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
139 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
140 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
141 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
142 vst1.8 {d4,d5},[r6] @128/8 = 16 bytes store
257 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
258 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
259 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
260 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
261 vst1.8 {d4,d5},[r6] @128/8 = 16 bytes store
[all …]
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| D | ihevc_itrans_recon_32x32.s | 122 @d5[0]= 50 d7[0]=18
123 @d5[1]= 46 d7[1]=13
124 @d5[2]= 43 d7[2]=9
125 @d5[3]= 38 d7[3]=4
172 vld1.16 {d4,d5,d6,d7},[r14]!
219 vmlal.s16 q15,d9,d5[1] @// y1 * sin1 - y3 * sin3(part of b3)
258 vmlal.s16 q13,d15,d5[1]
267 vmlal.s16 q8,d12,d5[0]
270 vmlsl.s16 q9,d13,d5[2]
334 vmlal.s16 q15,d15,d5[3]
[all …]
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| D | ihevc_inter_pred_filters_luma_vert.s | 163 vld1.u8 {d5},[r3],r2 @src_tmp2 = vld1_u8(pu1_src_tmp)@
168 vmlsl.u8 q4,d5,d27 @mul_res1 = vmlsl_u8(mul_res1, src_tmp2, coeffabs_5)@
187 vmlal.u8 q5,d5,d26 @mul_res2 = vmlal_u8(mul_res2, src_tmp2, coeffabs_4)@
206 vmlal.u8 q6,d5,d25
219 vmlsl.u8 q7,d5,d24
225 vld1.u8 {d5},[r3],r2 @src_tmp2 = vld1_u8(pu1_src_tmp)@
256 vmlsl.u8 q4,d5,d27 @mul_res1 = vmlsl_u8(mul_res1, src_tmp2, coeffabs_5)@
278 vmlal.u8 q5,d5,d26 @mul_res2 = vmlal_u8(mul_res2, src_tmp2, coeffabs_4)@
301 vmlal.u8 q6,d5,d25
325 vmlsl.u8 q7,d5,d24
[all …]
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| D | ihevc_intra_pred_luma_mode_3_to_9.s | 207 vsub.s8 d5, d9, d2 @ref_main_idx + 1 (row 1)
213 vtbl.8 d17, {d0,d1}, d5 @load from ref_main_idx + 1 (row 1)
225 vsub.s8 d5, d5, d3 @ref_main_idx + 1 (row 3)
234 vtbl.8 d11, {d0,d1}, d5 @load from ref_main_idx + 1 (row 3)
247 vsub.s8 d5, d5, d3 @ref_main_idx + 1 (row 5)
256 vtbl.8 d17, {d0,d1}, d5 @load from ref_main_idx + 1 (row 5)
269 vsub.s8 d5, d5, d3 @ref_main_idx + 1 (row 7)
278 vtbl.8 d11, {d0,d1}, d5 @load from ref_main_idx + 1 (row 7)
331 vtbl.8 d11, {d0,d1}, d5 @load from ref_main_idx - 1 (row 7)
351 vsub.s8 d5, d9, d2 @ref_main_idx - 1 (row 1)
[all …]
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| /external/tcpdump/tests/ |
| D | geonet_and_calm_fast.out | 2 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
5 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
8 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
11 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
14 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
20 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
28 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
31 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
34 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
37 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
[all …]
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| /external/libavc/common/arm/ |
| D | ih264_inter_pred_filters_luma_horz_a9q.s | 125 vld1.8 {d5, d6, d7}, [r0], r2 @// Load row1
128 vext.8 d28, d5, d6, #5 @//extract a[5] (column1,row1)
131 vaddl.u8 q7, d28, d5 @// a0 + a5 (column1,row1)
136 vext.8 d28, d5, d6, #2 @//extract a[2] (column1,row1)
144 vext.8 d28, d5, d6, #3 @//extract a[3] (column1,row1)
152 vext.8 d28, d5, d6, #1 @//extract a[1] (column1,row1)
160 vext.8 d28, d5, d6, #4 @//extract a[4] (column1,row1)
180 vld1.8 {d5, d6}, [r0], r2 @// Load row1
181 vext.8 d28, d5, d6, #5 @//extract a[5] (column1,row1)
183 vext.8 d25, d5, d6, #2 @//extract a[2] (column1,row1)
[all …]
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| D | ih264_inter_pred_luma_horz_qpel_a9q.s | 132 vld1.8 {d5, d6, d7}, [r0], r2 @// Load row1
135 vext.8 d28, d5, d6, #5 @//extract a[5] (column1,row1)
138 vaddl.u8 q7, d28, d5 @// a0 + a5 (column1,row1)
143 vext.8 d28, d5, d6, #2 @//extract a[2] (column1,row1)
151 vext.8 d28, d5, d6, #3 @//extract a[3] (column1,row1)
159 vext.8 d28, d5, d6, #1 @//extract a[1] (column1,row1)
167 vext.8 d28, d5, d6, #4 @//extract a[4] (column1,row1)
192 vld1.8 {d5, d6}, [r0], r2 @// Load row1
193 vext.8 d28, d5, d6, #5 @//extract a[5] (column1,row1)
195 vext.8 d25, d5, d6, #2 @//extract a[2] (column1,row1)
[all …]
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| D | ih264_inter_pred_luma_horz_hpel_vert_qpel_a9q.s | 152 vext.8 d5, d0, d1, #5
153 vaddl.u8 q3, d0, d5
164 vext.8 d5, d0, d1, #5
165 vaddl.u8 q4, d0, d5
178 vext.8 d5, d0, d1, #5
179 vaddl.u8 q5, d0, d5
192 vext.8 d5, d0, d1, #5
193 vaddl.u8 q6, d0, d5
206 vext.8 d5, d0, d1, #5
207 vaddl.u8 q7, d0, d5
[all …]
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| /external/valgrind/none/tests/arm/ |
| D | neon64.c | 645 TESTINSN_imm("vmov.i32 d5", d5, 0x700); in main()
660 TESTINSN_imm("vmvn.i32 d5", d5, 0x700); in main()
681 TESTINSN_imm("vbic.i32 d5", d5, 0x700); in main()
735 TESTINSN_bin("vand d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); in main()
742 TESTINSN_bin("vbic d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); in main()
763 TESTINSN_bin("veor d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); in main()
774 TESTINSN_bin("vbsl d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); in main()
785 TESTINSN_bin("vbit d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); in main()
796 TESTINSN_bin("vbif d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); in main()
811 TESTINSN_bin("vext.8 d0, d5, d15, #5", d0, d5, i8, 0x77, d15, i8, 0xff); in main()
[all …]
|
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| D | loopfilter_4_neon.asm | 55 vld1.u8 {d5}, [r2@64], r1 ; p1
68 vst1.u8 {d5}, [r3@64], r1 ; store op0
115 vld1.u8 {d5}, [r2], r1
125 vtrn.32 d5, d17
128 vtrn.16 d3, d5
134 vtrn.8 d5, d6
143 vst4.8 {d4[0], d5[0], d6[0], d7[0]}, [r0], r1
144 vst4.8 {d4[1], d5[1], d6[1], d7[1]}, [r0], r1
145 vst4.8 {d4[2], d5[2], d6[2], d7[2]}, [r0], r1
146 vst4.8 {d4[3], d5[3], d6[3], d7[3]}, [r0], r1
[all …]
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| D | loopfilter_8_neon.asm | 53 vld1.u8 {d5}, [r3@64], r1 ; p1
70 vst1.u8 {d5}, [r3@64], r1 ; store oq2
111 vld1.u8 {d5}, [r2], r1
121 vtrn.32 d5, d17
124 vtrn.16 d3, d5
130 vtrn.8 d5, d6
150 vst2.8 {d4[0], d5[0]}, [r3], r1
151 vst2.8 {d4[1], d5[1]}, [r3], r1
152 vst2.8 {d4[2], d5[2]}, [r3], r1
153 vst2.8 {d4[3], d5[3]}, [r3], r1
[all …]
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| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions-v8.1a.s | 16 vqrdmlsh.f64 d3, d5, d5
72 vqrdmlsh.s16 d7, d6, d5
103 vqrdmlsh.f32 q3, q4, d5[1]
104 vqrdmlsh.f64 d3, d5, d5[0]
|
| D | neon-vld-encoding.s | 12 vld1.16 {d4, d5, d6}, [r3:64]
13 vld1.32 {d5, d6, d7}, [r3]
16 vld1.16 {d4, d5, d6, d7}, [r3:64]
17 vld1.32 {d5, d6, d7, d8}, [r3]
39 vld1.16 {d4, d5, d6}, [r3:64]!
40 vld1.32 {d5, d6, d7}, [r3]!
44 vld1.16 {d4, d5, d6}, [r3:64], r6
45 vld1.32 {d5, d6, d7}, [r3], r6
49 vld1.16 {d4, d5, d6, d7}, [r3:64]!
50 vld1.32 {d5, d6, d7, d8}, [r3]!
[all …]
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| D | neon-mul-encoding.s | 111 vmul.u32 d5, d4[0]
112 vmul.f32 d6, d5[1]
120 vmul.f32 q6, d5[1]
126 vmul.s32 d5, d4, d3[1]
127 vmul.u32 d4, d5, d4[0]
128 vmul.f32 d3, d6, d5[1]
136 vmul.f32 q3, q6, d5[1]
143 @ CHECK: vmul.i32 d5, d5, d4[0] @ encoding: [0x44,0x58,0xa5,0xf2]
144 @ CHECK: vmul.f32 d6, d6, d5[1] @ encoding: [0x65,0x69,0xa6,0xf2]
152 @ CHECK: vmul.f32 q6, q6, d5[1] @ encoding: [0x65,0xc9,0xac,0xf3]
[all …]
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| D | thumb-neon-v8.s | 3 vmaxnm.f32 d4, d5, d1
4 @ CHECK: vmaxnm.f32 d4, d5, d1 @ encoding: [0x05,0xff,0x11,0x4f]
7 vminnm.f32 d5, d4, d30
8 @ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x24,0xff,0x3e,0x5f]
32 vcvtn.u32.f32 d5, d3
33 @ CHECK: vcvtn.u32.f32 d5, d3 @ encoding: [0xbb,0xff,0x83,0x51]
52 vrintx.f32 d5, d12
53 @ CHECK: vrintx.f32 d5, d12 @ encoding: [0xba,0xff,0x8c,0x54]
|
| D | neon-v8.s | 3 vmaxnm.f32 d4, d5, d1
4 @ CHECK: vmaxnm.f32 d4, d5, d1 @ encoding: [0x11,0x4f,0x05,0xf3]
7 vminnm.f32 d5, d4, d30
8 @ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x3e,0x5f,0x24,0xf3]
32 vcvtn.u32.f32 d5, d3
33 @ CHECK: vcvtn.u32.f32 d5, d3 @ encoding: [0x83,0x51,0xbb,0xf3]
52 vrintx.f32 d5, d12
53 @ CHECK: vrintx.f32 d5, d12 @ encoding: [0x8c,0x54,0xba,0xf3]
|
| D | single-precision-fp.s | 7 vdiv.f64 d4, d5, d6
15 @ CHECK-ERRORS-NEXT: vdiv.f64 d4, d5, d6
23 vnmla.f64 d5, d4, d3
26 vfms.f64 d4, d5, d6
34 @ CHECK-ERRORS-NEXT: vnmla.f64 d5, d4, d3
40 @ CHECK-ERRORS-NEXT: vfms.f64 d4, d5, d6
58 vabs.f64 d4, d5
59 vcmpe.f64 d5, #0
66 @ CHECK-ERRORS-NEXT: vabs.f64 d4, d5
68 @ CHECK-ERRORS-NEXT: vcmpe.f64 d5, #0
[all …]
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| /external/v8/test/mjsunit/ |
| D | generated-transition-stub.js | 208 d5 = [, 2.5, ,];
210 d5[i] = 0;
212 assertTrue(%HasFastDoubleElements(d5));
213 assertTrue(%HasFastHoleyElements(d5));
214 transition4(d5, 0, new Array(5));
215 assertTrue(%HasFastHoleyElements(d5));
216 assertTrue(%HasFastObjectElements(d5));
217 assertEquals(5, d5[0].length);
218 assertEquals(undefined, d5[2]);
|
| /external/libvpx/libvpx/vp8/common/arm/neon/ |
| D | shortidct4x4llm_neon.c | 25 int16x4_t d2, d3, d4, d5, d10, d11, d12, d13; in vp8_short_idct4x4llm_neon() local
34 d5 = vld1_s16(input + 12); in vp8_short_idct4x4llm_neon()
38 q2s16 = vcombine_s16(d3, d5); in vp8_short_idct4x4llm_neon()
58 d5 = vqsub_s16(d12, d11); in vp8_short_idct4x4llm_neon()
61 v2tmp1 = vtrn_s32(vreinterpret_s32_s16(d3), vreinterpret_s32_s16(d5)); in vp8_short_idct4x4llm_neon()
89 d5 = vqsub_s16(d12, d11); in vp8_short_idct4x4llm_neon()
94 d5 = vrshr_n_s16(d5, 3); in vp8_short_idct4x4llm_neon()
97 v2tmp1 = vtrn_s32(vreinterpret_s32_s16(d3), vreinterpret_s32_s16(d5)); in vp8_short_idct4x4llm_neon()
|
| /external/v8/test/mjsunit/asm/ |
| D | do-while-false.js | 35 function d5(a) { function in Module
53 return {d0: d0, d1: d1, d2: d2, d3: d3, d4: d4, d5: d5, d6: d6};
70 assertEquals(118, m.d5(1));
71 assertEquals(119, m.d5(0));
|
| /external/libpng/arm/ |
| D | filter_neon.S | 69 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
71 vadd.u8 d1, d0, d5
89 vext.8 d5, d22, d23, #3
92 vadd.u8 d1, d0, d5
124 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
129 vadd.u8 d1, d1, d5
151 vext.8 d5, d22, d23, #3
158 vadd.u8 d1, d1, d5
197 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
202 vadd.u8 d1, d1, d5
[all …]
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| /external/kernel-headers/original/uapi/linux/ |
| D | uuid.h | 35 #define UUID_LE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ argument
40 (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
42 #define UUID_BE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ argument
47 (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
|
| /external/libhevc/decoder/arm/ |
| D | ihevcd_itrans_recon_dc_luma.s | 96 vld1.8 d5,[r7],r2
109 vaddw.u8 q12,q0,d5
119 vqmovun.s16 d5,q12
129 vst1.u32 {d5},[r11],r3
160 vld1.8 d5,[r0]
168 vaddw.u8 q12,q0,d5
175 vqmovun.s16 d5,q12
182 vst1.u32 {d5[0]},[r1]
|