| /external/llvm/test/CodeGen/X86/ |
| D | misched-aa-mmos.ll | 3 ; This generates a decw instruction, which has two MMOs, and an alias SU edge
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| D | lsr-wrap.ll | 7 ; CHECK: decw %
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| D | atomic_add.ll | 178 ; CHECK: decw
180 ; SLOW_INC-NOT: decw
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| D | atomic16.ll | 41 ; X64: decw
43 ; X32: decw
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| D | rd-mod-wr-eflags.ll | 97 ; CHECK: decw {{[0-9][0-9]*}}({{.*}})
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| D | atomic_mi.ll | 782 ; X64-NOT: decw
784 ; X32-NOT: decw
786 ; SLOW_INC-NOT: decw
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| /external/ImageMagick/MagickCore/ |
| D | Make.com | 10 $if (f$trnlnm("X11") .eqs. "") then define/nolog X11 decw$include:
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| /external/llvm/test/MC/X86/ |
| D | x86-16.s | 553 decw %ax
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| D | x86-32.s | 643 decw %ax
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| D | x86-64.s | 950 decw %ax // CHECK: decw %ax # encoding: [0x66,0xff,0xc8] label
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| D | x86-32-coverage.s | 505 decw 0x7eed
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| /external/ImageMagick/ |
| D | Magickshr.opt | 212 sys$share:decw$xlibshr.exe/share
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| /external/ImageMagick/coders/ |
| D | Make.com | 7 $if (f$trnlnm("X11") .eqs. "") then define/nolog X11 decw$include:
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| /external/valgrind/none/tests/x86/ |
| D | x86locked.c | 460 GEN_do_locked_unary_E(decw,ax)
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| D | insn_basic.def | 425 decw r16.uw[12345] => 0.uw[12344]
426 decw m16.uw[12345] => 0.uw[12344]
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| /external/valgrind/none/tests/amd64/ |
| D | amd64locked.c | 496 GEN_do_locked_unary_E(decw,ax)
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| D | insn_basic.def | 558 decw r16.uw[12345] => 0.uw[12344]
559 decw m16.uw[12345] => 0.uw[12344]
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| /external/llvm/test/MC/Disassembler/X86/ |
| D | x86-64.txt | 215 # CHECK: decw %cx
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| D | x86-16.txt | 510 # CHECK: decw %ax
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| D | x86-32.txt | 703 # CHECK: decw %cx
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| /external/mesa3d/include/GL/ |
| D | vms_x_fix.h | 15 #define decw$_select DECW$_SELECT
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| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 428 #define DEC_W(a) CHOICE(decw a, decw a, _WTOG dec a)
|
| /external/valgrind/perf/ |
| D | tinycc.c | 3287 ALT(DEF_ASM_OP1(decw, 0x48, 0, OPC_REG | OPC_WL, OPT_REGW))
3744 ALT(DEF_ASM_OP1(decw, 0x48, 0, OPC_REG | OPC_WL, OPT_REGW))
4619 ALT(DEF_ASM_OP1(decw, 0x48, 0, OPC_REG | OPC_WL, OPT_REGW))
5076 ALT(DEF_ASM_OP1(decw, 0x48, 0, OPC_REG | OPC_WL, OPT_REGW))
15326 ALT(DEF_ASM_OP1(decw, 0x48, 0, OPC_REG | OPC_WL, OPT_REGW))
15788 ALT(DEF_ASM_OP1(decw, 0x48, 0, OPC_REG | OPC_WL, OPT_REGW))
|
| /external/elfutils/tests/ |
| D | testfile44.expect.bz2 | 1testfile44.o: elf32-elf_i386
2
3Disassembly of section .text:
4
5 0 ... |
| D | testfile45.expect.bz2 | 1testfile45.o: elf64-elf_x86_64
2
3Disassembly of section .text:
4
5 0 ... |