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Searched refs:divdu (Results 1 – 9 of 9) sorted by relevance

/external/llvm/test/MC/PowerPC/
Dppc64-encoding.s481 # CHECK-BE: divdu 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x92]
482 # CHECK-LE: divdu 2, 3, 4 # encoding: [0x92,0x23,0x43,0x7c]
483 divdu 2, 3, 4
484 # CHECK-BE: divdu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x93]
485 # CHECK-LE: divdu. 2, 3, 4 # encoding: [0x93,0x23,0x43,0x7c]
486 divdu. 2, 3, 4
/external/valgrind/none/tests/ppc64/
Djm-int.stdout.exp-LE200 divdu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
201 divdu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
202 divdu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
203 divdu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
204 divdu 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
205 divdu 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
206 divdu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
207 divdu ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (00000000 00000000)
208 divdu ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
429 divdu. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
[all …]
Djm-int.stdout.exp200 divdu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
201 divdu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
202 divdu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
203 divdu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
204 divdu 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
205 divdu 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
206 divdu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
207 divdu ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (00000000 00000000)
208 divdu ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64le-encoding.txt376 # CHECK: divdu 2, 3, 4
379 # CHECK: divdu. 2, 3, 4
Dppc64-encoding.txt376 # CHECK: divdu 2, 3, 4
379 # CHECK: divdu. 2, 3, 4
/external/v8/src/compiler/ppc/
Dcode-generator-ppc.cc1237 __ divdu(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); in AssembleArchInstruction() local
1257 ASSEMBLE_MODULO(divdu, mulld); in AssembleArchInstruction()
/external/v8/src/ppc/
Dassembler-ppc.h929 void divdu(Register dst, Register src1, Register src2, OEBit o = LeaveOE,
Dassembler-ppc.cc1527 void Assembler::divdu(Register dst, Register src1, Register src2, OEBit o, in divdu() function in v8::internal::Assembler
/external/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td630 "divdu", "$rT, $rA, $rB", IIC_IntDivD,