Searched refs:divwu (Results 1 – 12 of 12) sorted by relevance
427 # CHECK-BE: divwu 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x96]428 # CHECK-LE: divwu 2, 3, 4 # encoding: [0x96,0x23,0x43,0x7c]429 divwu 2, 3, 4430 # CHECK-BE: divwu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x97]431 # CHECK-LE: divwu. 2, 3, 4 # encoding: [0x97,0x23,0x43,0x7c]432 divwu. 2, 3, 4
334 # CHECK: divwu 2, 3, 4337 # CHECK: divwu. 2, 3, 4
334 # CHECK: divwu 2, 3, 4 337 # CHECK: divwu. 2, 3, 4
56 divwu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)57 divwu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)58 divwu 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)59 divwu 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)60 divwu ffffffffffffffff, 0000001cbe991def => 0000000000000001 (00000000 00000000)61 divwu ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)285 divwu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)286 divwu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)287 divwu. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)288 divwu. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)[all …]
56 divwu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)57 divwu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)58 divwu 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)59 divwu 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)60 divwu ffffffffffffffff, 0000001cbe991def => 0000000000000001 (00000000 00000000)61 divwu ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
56 divwu 00000000, 000f423f => 00000000 (00000000 00000000)57 divwu 00000000, ffffffff => 00000000 (00000000 00000000)58 divwu 000f423f, 000f423f => 00000001 (00000000 00000000)59 divwu 000f423f, ffffffff => 00000000 (00000000 00000000)60 divwu ffffffff, 000f423f => 000010c6 (00000000 00000000)61 divwu ffffffff, ffffffff => 00000001 (00000000 00000000)
1232 __ divwu(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); in AssembleArchInstruction() local1253 ASSEMBLE_MODULO(divwu, mullw); in AssembleArchInstruction()
837 void divwu(Register dst, Register src1, Register src2, OEBit o = LeaveOE,
937 void Assembler::divwu(Register dst, Register src1, Register src2, OEBit o, in divwu() function in v8::internal::Assembler
2372 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
42782 0x2547DDC8: 7D205B96 divwu r9, r0, r1147467 0x254782A8: 7D8E0396 divwu r12, r14, r075892 0xFE87D48: 7CD9D396 divwu r6, r25, r2675906 0xFE87D50: 7F993B96 divwu r28, r25, r7123218 0x100065B4: 7D202B96 divwu r9, r0, r5129889 0xFECA7C4: 7C994B96 divwu r4, r25, r9
39672 0x2547DDC8: 7D205B96 divwu r9, r0, r1143247 0x254782A8: 7D8E0396 divwu r12, r14, r0