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/external/llvm/test/MC/ARM/
Dthumb-neon-v8.s3 vmaxnm.f32 d4, d5, d1
4 @ CHECK: vmaxnm.f32 d4, d5, d1 @ encoding: [0x05,0xff,0x11,0x4f]
5 vmaxnm.f32 q2, q4, q6
6 @ CHECK: vmaxnm.f32 q2, q4, q6 @ encoding: [0x08,0xff,0x5c,0x4f]
7 vminnm.f32 d5, d4, d30
8 @ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x24,0xff,0x3e,0x5f]
9 vminnm.f32 q0, q13, q2
10 @ CHECK: vminnm.f32 q0, q13, q2 @ encoding: [0x2a,0xff,0xd4,0x0f]
12 vcvta.s32.f32 d4, d6
13 @ CHECK: vcvta.s32.f32 d4, d6 @ encoding: [0xbb,0xff,0x06,0x40]
[all …]
Dneon-v8.s3 vmaxnm.f32 d4, d5, d1
4 @ CHECK: vmaxnm.f32 d4, d5, d1 @ encoding: [0x11,0x4f,0x05,0xf3]
5 vmaxnm.f32 q2, q4, q6
6 @ CHECK: vmaxnm.f32 q2, q4, q6 @ encoding: [0x5c,0x4f,0x08,0xf3]
7 vminnm.f32 d5, d4, d30
8 @ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x3e,0x5f,0x24,0xf3]
9 vminnm.f32 q0, q13, q2
10 @ CHECK: vminnm.f32 q0, q13, q2 @ encoding: [0xd4,0x0f,0x2a,0xf3]
12 vcvta.s32.f32 d4, d6
13 @ CHECK: vcvta.s32.f32 d4, d6 @ encoding: [0x06,0x40,0xbb,0xf3]
[all …]
Dneon-convert-encoding.s3 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
4 vcvt.s32.f32 d16, d16
5 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3]
6 vcvt.u32.f32 d16, d16
7 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3]
8 vcvt.f32.s32 d16, d16
9 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3]
10 vcvt.f32.u32 d16, d16
11 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3]
12 vcvt.s32.f32 q8, q8
[all …]
Dneont2-convert-encoding.s5 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
6 vcvt.s32.f32 d16, d16
7 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07]
8 vcvt.u32.f32 d16, d16
9 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
10 vcvt.f32.s32 d16, d16
11 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06]
12 vcvt.f32.u32 d16, d16
13 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
14 vcvt.s32.f32 q8, q8
[all …]
Dneont2-cmp-encoding.s5 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
6 vcvt.s32.f32 d16, d16
7 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07]
8 vcvt.u32.f32 d16, d16
9 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
10 vcvt.f32.s32 d16, d16
11 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06]
12 vcvt.f32.u32 d16, d16
13 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
14 vcvt.s32.f32 q8, q8
[all …]
Dthumb-fp-armv8.s31 vcvta.s32.f32 s2, s3
32 @ CHECK: vcvta.s32.f32 s2, s3 @ encoding: [0xbc,0xfe,0xe1,0x1a]
35 vcvtn.s32.f32 s6, s23
36 @ CHECK: vcvtn.s32.f32 s6, s23 @ encoding: [0xbd,0xfe,0xeb,0x3a]
39 vcvtp.s32.f32 s0, s4
40 @ CHECK: vcvtp.s32.f32 s0, s4 @ encoding: [0xbe,0xfe,0xc2,0x0a]
43 vcvtm.s32.f32 s17, s8
44 @ CHECK: vcvtm.s32.f32 s17, s8 @ encoding: [0xff,0xfe,0xc4,0x8a]
48 vcvta.u32.f32 s2, s3
49 @ CHECK: vcvta.u32.f32 s2, s3 @ encoding: [0xbc,0xfe,0x61,0x1a]
[all …]
Dfp-armv8.s28 vcvta.s32.f32 s2, s3
29 @ CHECK: vcvta.s32.f32 s2, s3 @ encoding: [0xe1,0x1a,0xbc,0xfe]
32 vcvtn.s32.f32 s6, s23
33 @ CHECK: vcvtn.s32.f32 s6, s23 @ encoding: [0xeb,0x3a,0xbd,0xfe]
36 vcvtp.s32.f32 s0, s4
37 @ CHECK: vcvtp.s32.f32 s0, s4 @ encoding: [0xc2,0x0a,0xbe,0xfe]
40 vcvtm.s32.f32 s17, s8
41 @ CHECK: vcvtm.s32.f32 s17, s8 @ encoding: [0xc4,0x8a,0xff,0xfe]
45 vcvta.u32.f32 s2, s3
46 @ CHECK: vcvta.u32.f32 s2, s3 @ encoding: [0x61,0x1a,0xbc,0xfe]
[all …]
Dvfp4.s13 @ ARM: vfma.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0xa2,0xee]
14 @ THUMB: vfma.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x00,0x1a]
15 @ THUMB_V7EM: vfma.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x00,0x1a]
16 vfma.f32 s2, s4, s0
18 @ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2]
19 @ THUMB: vfma.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0c]
21 @ THUMB_V7EM-ERRORS-NEXT: vfma.f32 d16, d18, d17
22 vfma.f32 d16, d18, d17
24 @ ARM: vfma.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x08,0xf2]
25 @ THUMB: vfma.f32 q2, q4, q0 @ encoding: [0x08,0xef,0x50,0x4c]
[all …]
Ddirective-arch_extension-simd.s19 vmaxnm.f32 s0, s0, s0
21 vminnm.f32 s0, s0, s0
29 vcvta.s32.f32 s0, s0
31 vcvta.u32.f32 s0, s0
37 vcvtn.s32.f32 s0, s0
39 vcvtn.u32.f32 s0, s0
45 vcvtp.s32.f32 s0, s0
47 vcvtp.u32.f32 s0, s0
53 vcvtm.s32.f32 s0, s0
55 vcvtm.u32.f32 s0, s0
[all …]
Ddirective-arch_extension-fp.s22 vselgt.f32 s0, s0, s0
24 vselge.f32 s0, s0, s0
26 vseleq.f32 s0, s0, s0
28 vselvs.f32 s0, s0, s0
30 vmaxnm.f32 s0, s0, s0
32 vminnm.f32 s0, s0, s0
57 vcvta.s32.f32 s0, s0
59 vcvta.u32.f32 s0, s0
65 vcvtn.s32.f32 s0, s0
67 vcvtn.u32.f32 s0, s0
[all …]
Dneon-reciprocal-encoding.s7 @ CHECK: vrecpe.f32 d16, d16 @ encoding: [0x20,0x05,0xfb,0xf3]
8 vrecpe.f32 d16, d16
9 @ CHECK: vrecpe.f32 q8, q8 @ encoding: [0x60,0x05,0xfb,0xf3]
10 vrecpe.f32 q8, q8
11 @ CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x40,0xf2]
12 vrecps.f32 d16, d16, d17
13 @ CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x40,0xf2]
14 vrecps.f32 q8, q8, q9
19 @ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xa0,0x05,0xfb,0xf3]
20 vrsqrte.f32 d16, d16
[all …]
Dpr22395.s15 vadd.f32 s1, s2, s3
16 @ CHECK: vadd.f32 s1, s2, s3
20 vadd.f32 s1, s2, s3
21 @ CHECK: vadd.f32 s1, s2, s3
25 vadd.f32 s1, s2, s3
26 @ CHECK: vadd.f32 s1, s2, s3
30 vadd.f32 s1, s2, s3
31 @ CHECK: vadd.f32 s1, s2, s3
35 vadd.f32 s1, s2, s3
36 @ CHECK: vadd.f32 s1, s2, s3
[all …]
Dneont2-reciprocal-encoding.s9 @ CHECK: vrecpe.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x05]
10 vrecpe.f32 d16, d16
11 @ CHECK: vrecpe.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x05]
12 vrecpe.f32 q8, q8
13 @ CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0x40,0xef,0xb1,0x0f]
14 vrecps.f32 d16, d16, d17
15 @ CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x0f]
16 vrecps.f32 q8, q8, q9
21 @ CHECK: vrsqrte.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x05]
22 vrsqrte.f32 d16, d16
[all …]
Dinvalid-fp-armv8.s10 vsel.f32 s3, s4, s6
12 vselne.f32 s3, s4, s6
14 vselmi.f32 s3, s4, s6
16 vselpl.f32 s3, s4, s6
18 vselvc.f32 s3, s4, s6
20 vselcs.f32 s3, s4, s6
22 vselcc.f32 s3, s4, s6
24 vselhs.f32 s3, s4, s6
26 vsello.f32 s3, s4, s6
28 vselhi.f32 s3, s4, s6
[all …]
Dsimple-fp-encoding.s4 vadd.f32 s0, s1, s0
6 @ CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee]
9 vsub.f32 s0, s1, s0
11 @ CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee]
14 vdiv.f32 s0, s1, s0
15 vdiv.f32 s5, s7
19 @ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
20 @ CHECK: vdiv.f32 s5, s5, s7 @ encoding: [0xa3,0x2a,0xc2,0xee]
26 vmul.f32 s0, s1, s0
27 vmul.f32 s11, s21
[all …]
/external/clang/test/CodeGen/
Dtbaa.cpp12 uint32_t f32; member
20 uint32_t f32; member
26 uint32_t f32; member
32 uint32_t f32; member
39 uint32_t f32; member
44 uint32_t f32; member
55 A->f32 = 4; in g()
78 A->f32 = 1; in g3()
79 B->a.f32 = 4; in g3()
80 return A->f32; in g3()
[all …]
Dtbaa-class.cpp13 uint32_t f32; member in StructA
22 uint32_t f32; member in StructB
29 uint32_t f32; member in StructC
36 uint32_t f32; member in StructD
44 uint32_t f32; member in StructS
61 A->f32 = 4; in g()
84 A->f32 = 1; in g3()
85 B->a.f32 = 4; in g3()
86 return A->f32; in g3()
96 A->f32 = 1; in g4()
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dthumb-neon-v8.txt4 # CHECK: vmaxnm.f32 d4, d5, d1
6 # CHECK: vmaxnm.f32 q2, q4, q6
8 # CHECK: vminnm.f32 d5, d4, d30
10 # CHECK: vminnm.f32 q0, q13, q2
13 # CHECK: vcvta.s32.f32 d4, d6
15 # CHECK: vcvta.u32.f32 d12, d10
17 # CHECK: vcvta.s32.f32 q4, q6
19 # CHECK: vcvta.u32.f32 q4, q10
22 # CHECK: vcvtm.s32.f32 d1, d30
24 # CHECK: vcvtm.u32.f32 d12, d10
[all …]
Dneon-v8.txt4 # CHECK: vmaxnm.f32 d4, d5, d1
6 # CHECK: vmaxnm.f32 q2, q4, q6
8 # CHECK: vminnm.f32 d5, d4, d30
10 # CHECK: vminnm.f32 q0, q13, q2
13 # CHECK: vcvta.s32.f32 d4, d6
15 # CHECK: vcvta.u32.f32 d12, d10
17 # CHECK: vcvta.s32.f32 q4, q6
19 # CHECK: vcvta.u32.f32 q4, q10
22 # CHECK: vcvtm.s32.f32 d1, d30
24 # CHECK: vcvtm.u32.f32 d12, d10
[all …]
/external/mesa3d/src/gallium/auxiliary/util/
Du_half.h55 union fi f32; in util_float_to_half() local
60 f32.f = f; in util_float_to_half()
63 sign = f32.ui & sign_mask; in util_float_to_half()
64 f32.ui ^= sign; in util_float_to_half()
66 if (f32.ui == f32inf) { in util_float_to_half()
69 } else if (f32.ui > f32inf) { in util_float_to_half()
74 f32.ui &= round_mask; in util_float_to_half()
75 f32.f *= magic.f; in util_float_to_half()
76 f32.ui -= round_mask; in util_float_to_half()
79 if (f32.ui > f16inf) in util_float_to_half()
[all …]
Du_format_r11g11b10f.h53 } f32 = {val}; in f32_to_uf11() local
58 int sign = (f32.ui >> 16) & 0x8000; in f32_to_uf11()
60 int exponent = ((f32.ui >> 23) & 0xff) - 127; in f32_to_uf11()
61 int mantissa = f32.ui & 0x007fffff; in f32_to_uf11()
102 } f32; in uf11_to_f32() local
107 f32.f = 0.0; in uf11_to_f32()
112 f32.f = scale * mantissa; in uf11_to_f32()
116 f32.ui = F32_INFINITY | mantissa; in uf11_to_f32()
128 f32.f = scale * decimal; in uf11_to_f32()
131 return f32.f; in uf11_to_f32()
[all …]
/external/llvm/test/CodeGen/Thumb2/
Dfloat-intrinsics-float.ll8 declare float @llvm.sqrt.f32(float %Val)
12 ; HARD: vsqrt.f32 s0, s0
13 %1 = call float @llvm.sqrt.f32(float %a)
17 declare float @llvm.powi.f32(float %Val, i32 %power)
22 %1 = call float @llvm.powi.f32(float %a, i32 %b)
26 declare float @llvm.sin.f32(float %Val)
31 %1 = call float @llvm.sin.f32(float %a)
35 declare float @llvm.cos.f32(float %Val)
40 %1 = call float @llvm.cos.f32(float %a)
44 declare float @llvm.pow.f32(float %Val, float %power)
[all …]
/external/llvm/test/CodeGen/ARM/
Dfmacs.ll10 ; VFP2: vmla.f32
13 ; NEON: vmla.f32
16 ; A8: vmul.f32
17 ; A8: vadd.f32
42 ; VFP2: vmla.f32
45 ; NEON: vmla.f32
48 ; A8: vmul.f32
49 ; A8: vadd.f32
60 ; A8: vmul.f32
61 ; A8: vmul.f32
[all …]
/external/llvm/test/CodeGen/WebAssembly/
Dcomparisons_f32.ll10 ; CHECK-NEXT: .param f32, f32{{$}}
12 ; CHECK-NEXT: f32.eq $push[[NUM0:[0-9]+]]=, $0, $0{{$}}
13 ; CHECK-NEXT: f32.eq $push[[NUM1:[0-9]+]]=, $1, $1{{$}}
23 ; CHECK-NEXT: .param f32, f32{{$}}
25 ; CHECK-NEXT: f32.ne $push[[NUM0:[0-9]+]]=, $0, $0{{$}}
26 ; CHECK-NEXT: f32.ne $push[[NUM1:[0-9]+]]=, $1, $1{{$}}
36 ; CHECK-NEXT: .param f32, f32{{$}}
38 ; CHECK-NEXT: f32.eq $push[[NUM:[0-9]+]]=, $0, $1{{$}}
47 ; CHECK: f32.ne $push[[NUM:[0-9]+]]=, $0, $1{{$}}
56 ; CHECK: f32.lt $push[[NUM:[0-9]+]]=, $0, $1{{$}}
[all …]
Df32.ll8 declare float @llvm.fabs.f32(float)
9 declare float @llvm.copysign.f32(float, float)
10 declare float @llvm.sqrt.f32(float)
11 declare float @llvm.ceil.f32(float)
12 declare float @llvm.floor.f32(float)
13 declare float @llvm.trunc.f32(float)
14 declare float @llvm.nearbyint.f32(float)
15 declare float @llvm.rint.f32(float)
16 declare float @llvm.fma.f32(float, float, float)
19 ; CHECK-NEXT: .param f32, f32{{$}}
[all …]

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