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Searched refs:getSizeInBits (Results 1 – 25 of 86) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DValueTypes.h84 unsigned BitWidth = EltTy.getSizeInBits(); in changeVectorElementTypeToInteger()
100 return MVT::getIntegerVT(getSizeInBits()); in changeTypeToInteger()
179 return (getSizeInBits() & 7) == 0; in isByteSized()
184 unsigned BitSize = getSizeInBits(); in isRound()
191 return getSizeInBits() == VT.getSizeInBits(); in bitsEq()
197 return getSizeInBits() > VT.getSizeInBits(); in bitsGT()
203 return getSizeInBits() >= VT.getSizeInBits(); in bitsGE()
209 return getSizeInBits() < VT.getSizeInBits(); in bitsLT()
215 return getSizeInBits() <= VT.getSizeInBits(); in bitsLE()
251 unsigned getSizeInBits() const { in getSizeInBits() function
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DMachineValueType.h422 unsigned getSizeInBits() const { in getSizeInBits() function
509 return getScalarType().getSizeInBits(); in getScalarSizeInBits()
515 return (getSizeInBits() + 7) / 8; in getStoreSize()
526 return getSizeInBits() > VT.getSizeInBits(); in bitsGT()
531 return getSizeInBits() >= VT.getSizeInBits(); in bitsGE()
536 return getSizeInBits() < VT.getSizeInBits(); in bitsLT()
541 return getSizeInBits() <= VT.getSizeInBits(); in bitsLE()
DBasicTTIImpl.h347 SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) { in getCastInstrCost()
388 SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) { in getCastInstrCost()
490 Src->getPrimitiveSizeInBits() < LT.second.getSizeInBits()) { in getMemoryOpCost()
/external/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.cpp83 unsigned VectorSizeInBits = VT.getSizeInBits(); in DecodeMOVDDUPMask()
97 unsigned VectorSizeInBits = VT.getSizeInBits(); in DecodePSLLDQMask()
111 unsigned VectorSizeInBits = VT.getSizeInBits(); in DecodePSRLDQMask()
128 unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8); in DecodePALIGNRMask()
130 unsigned NumLanes = VT.getSizeInBits() / 128; in DecodePALIGNRMask()
149 unsigned NumLanes = VT.getSizeInBits() / 128; in DecodePSHUFMask()
211 unsigned NumLanes = VT.getSizeInBits() / 128; in DecodeSHUFPMask()
235 unsigned NumLanes = VT.getSizeInBits() / 128; in DecodeUNPCKHMask()
255 unsigned NumLanes = VT.getSizeInBits() / 128; in DecodeUNPCKLMask()
272 unsigned NumLanes = VT.getSizeInBits() / 128; in decodeVSHUF64x2FamilyMask()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp564 unsigned SrcEltBits = SrcEltVT.getSizeInBits(); in ExpandLoad()
569 unsigned WideBits = WideVT.getSizeInBits(); in ExpandLoad()
617 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8; in ExpandLoad()
666 unsigned ScalarSize = MemSclVT.getSizeInBits(); in ExpandStore()
761 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, in ExpandSELECT()
776 APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy); in ExpandSELECT()
796 unsigned BW = VT.getScalarType().getSizeInBits(); in ExpandSEXTINREG()
797 unsigned OrigBW = OrigTy.getScalarType().getSizeInBits(); in ExpandSEXTINREG()
843 unsigned EltWidth = VT.getVectorElementType().getSizeInBits(); in ExpandSIGN_EXTEND_VECTOR_INREG()
844 unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits(); in ExpandSIGN_EXTEND_VECTOR_INREG()
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DLegalizeTypes.cpp799 assert(Result.getValueType().getSizeInBits() >= in SetScalarizedVector()
800 Op.getValueType().getVectorElementType().getSizeInBits() && in SetScalarizedVector()
910 unsigned BitWidth = Op.getValueType().getSizeInBits(); in BitConvertToInteger()
919 unsigned EltWidth = Op.getValueType().getVectorElementType().getSizeInBits(); in BitConvertVectorToIntegerVector()
1032 unsigned EltSize = EltVT.getSizeInBits() / 8; // FIXME: should be ABI size. in GetVectorElementPointer()
1033 assert(EltSize * 8 == EltVT.getSizeInBits() && in GetVectorElementPointer()
1049 LVT.getSizeInBits() + HVT.getSizeInBits()); in JoinIntegers()
1054 DAG.getConstant(LVT.getSizeInBits(), dlHi, in JoinIntegers()
1153 assert(LoVT.getSizeInBits() + HiVT.getSizeInBits() == in SplitInteger()
1154 Op.getValueType().getSizeInBits() && "Invalid integer splitting!"); in SplitInteger()
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DTargetLowering.cpp394 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && in SimplifyDemandedBits()
658 unsigned InnerBits = InnerVT.getSizeInBits(); in SimplifyDemandedBits()
662 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) in SimplifyDemandedBits()
709 unsigned VTSize = VT.getSizeInBits(); in SimplifyDemandedBits()
785 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); in SimplifyDemandedBits()
828 unsigned ShAmt = ExVT.getScalarType().getSizeInBits(); in SimplifyDemandedBits()
830 unsigned VTBits = Op->getValueType(0).getScalarType().getSizeInBits(); in SimplifyDemandedBits()
854 BitWidth - ExVT.getScalarType().getSizeInBits()); in SimplifyDemandedBits()
861 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth); in SimplifyDemandedBits()
864 ExVT.getScalarType().getSizeInBits()) & in SimplifyDemandedBits()
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DLegalizeVectorTypes.cpp777 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits()); in SplitVecRes_BITCAST()
778 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits()); in SplitVecRes_BITCAST()
867 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; in SplitVecRes_INSERT_SUBVECTOR()
966 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; in SplitVecRes_INSERT_VECTOR_ELT()
1010 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; in SplitVecRes_LOAD()
1044 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ? in SplitVecRes_MLOAD()
1072 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; in SplitVecRes_MLOAD()
1234 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) { in SplitVecRes_ExtendOp()
1238 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2), in SplitVecRes_ExtendOp()
1586 if (EltVT.getSizeInBits() < 8) { in SplitVecOp_EXTRACT_VECTOR_ELT()
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DLegalizeIntegerTypes.cpp291 NOutVT.getSizeInBits()), in PromoteIntRes_BITCAST()
784 DAG.getIntPtrConstant(SmallVT.getSizeInBits(), in PromoteIntRes_XMULO()
839 DAG.getConstant(i * RegVT.getSizeInBits(), dl, in PromoteIntRes_VAARG()
1037 DAG.getConstant(OVT.getSizeInBits(), dl, in PromoteIntOp_BUILD_PAIR()
1054 assert(N->getOperand(0).getValueType().getSizeInBits() >= in PromoteIntOp_BUILD_VECTOR()
1055 N->getValueType(0).getVectorElementType().getSizeInBits() && in PromoteIntOp_BUILD_VECTOR()
1084 assert(N->getOperand(1).getValueType().getSizeInBits() >= in PromoteIntOp_INSERT_VECTOR_ELT()
1085 N->getValueType(0).getVectorElementType().getSizeInBits() && in PromoteIntOp_INSERT_VECTOR_ELT()
1428 unsigned VTBits = N->getValueType(0).getSizeInBits(); in ExpandShiftByConstant()
1429 unsigned NVTBits = NVT.getSizeInBits(); in ExpandShiftByConstant()
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DLegalizeDAG.cpp328 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); in ExpandUnalignedStore()
345 StoredVT.getSizeInBits())); in ExpandUnalignedStore()
346 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; in ExpandUnalignedStore()
347 unsigned RegBytes = RegVT.getSizeInBits() / 8; in ExpandUnalignedStore()
408 int NumBits = NewStoredVT.getSizeInBits(); in ExpandUnalignedStore()
452 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); in ExpandUnalignedLoad()
471 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; in ExpandUnalignedLoad()
472 unsigned RegBytes = RegVT.getSizeInBits() / 8; in ExpandUnalignedLoad()
538 unsigned NumBits = LoadedVT.getSizeInBits(); in ExpandUnalignedLoad()
627 unsigned EltSize = EltVT.getSizeInBits()/8; in PerformInsertVectorEltInMemory()
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DDAGCombiner.cpp183 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); in SimplifyDemandedBits()
763 EltVT.getSizeInBits() >= SplatBitSize); in isConstantSplatVector()
1758 unsigned DestBits = VT.getScalarType().getSizeInBits(); in visitADD()
2059 ConstValue1.getBitWidth() == VT.getScalarType().getSizeInBits(); in visitMUL()
2426 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, in visitREM()
2487 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, in visitMULHS()
2499 unsigned SimpleSize = Simple.getSizeInBits(); in visitMULHS()
2535 unsigned SimpleSize = Simple.getSizeInBits(); in visitMULHU()
2613 unsigned SimpleSize = Simple.getSizeInBits(); in visitSMUL_LOHI()
2644 unsigned SimpleSize = Simple.getSizeInBits(); in visitUMUL_LOHI()
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DSelectionDAG.cpp124 unsigned EltSize = N->getValueType(0).getVectorElementType().getSizeInBits(); in isBuildVectorAllOnes()
167 unsigned EltSize = N->getValueType(0).getVectorElementType().getSizeInBits(); in isBuildVectorAllZeros()
714 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && in VerifySDNode()
1043 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); in getZeroExtendInReg()
1045 VT.getSizeInBits()); in getZeroExtendInReg()
1052 assert(VT.getSizeInBits() == Op.getValueType().getSizeInBits() && in getAnyExtendVectorInReg()
1062 assert(VT.getSizeInBits() == Op.getValueType().getSizeInBits() && in getSignExtendVectorInReg()
1072 assert(VT.getSizeInBits() == Op.getValueType().getSizeInBits() && in getZeroExtendVectorInReg()
1085 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), DL, VT); in getNOT()
1098 TrueValue = getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), DL, in getLogicalNOT()
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DLegalizeTypesGeneric.cpp115 unsigned NewSizeInBits = ElemVT.getSizeInBits() / 2; in ExpandRes_BITCAST()
147 LHS.getValueType().getSizeInBits() << 1), in ExpandRes_BITCAST()
181 unsigned IncrementSize = NOutVT.getSizeInBits() / 8; in ExpandRes_BITCAST()
278 unsigned IncrementSize = NVT.getSizeInBits() / 8; in ExpandRes_NormalLoad()
486 unsigned IncrementSize = NVT.getSizeInBits() / 8; in ExpandOp_NormalStore()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp758 unsigned MemBits = VT.getScalarType().getSizeInBits(); in computeKnownBitsForTargetNode()
1862 if (VT.getSizeInBits() < InVT.getSizeInBits()) { in LowerVectorFP_TO_INT()
1870 if (VT.getSizeInBits() > InVT.getSizeInBits()) { in LowerVectorFP_TO_INT()
1920 if (VT.getSizeInBits() < InVT.getSizeInBits()) { in LowerVectorINT_TO_FP()
1928 if (VT.getSizeInBits() > InVT.getSizeInBits()) { in LowerVectorINT_TO_FP()
2019 if (OrigVT.getSizeInBits() >= 64) in getExtensionTo64Bits()
2043 if (OrigTy.getSizeInBits() >= 64) in addRequiredExtensionForVectorMULL()
2061 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); in isExtendedBUILD_VECTOR()
2088 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2; in skipExtensionForVectorMULL()
2481 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8; in LowerFormalArguments()
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DAArch64ISelDAGToDAG.cpp350 unsigned BitSize = N.getValueType().getSizeInBits(); in SelectShiftedRegister()
1193 bool Is128Bit = VT.getSizeInBits() == 128; in SelectStore()
1211 bool Is128Bit = VT.getSizeInBits() == 128; in SelectPostStore()
1263 bool Narrow = VT.getSizeInBits() == 64; in SelectLoadLane()
1303 bool Narrow = VT.getSizeInBits() == 64; in SelectPostLoadLane()
1359 bool Narrow = VT.getSizeInBits() == 64; in SelectStoreLane()
1389 bool Narrow = VT.getSizeInBits() == 64; in SelectPostStoreLane()
1490 if (!BiggerPattern && (Srl_imm <= 0 || Srl_imm >= VT.getSizeInBits())) { in isBitfieldExtractOpFromAnd()
1587 Trunc_bits = Opd0->getValueType(0).getSizeInBits() - VT.getSizeInBits(); in isBitfieldExtractOpFromShr()
1600 if (Shl_imm >= VT.getSizeInBits()) { in isBitfieldExtractOpFromShr()
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/external/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp119 : Opcode(Op), BitSize(N.getValueType().getSizeInBits()), in RxSBGOperands()
707 uint64_t Used = allOnes(Op.getValueType().getSizeInBits()); in detectOrAndInsertion()
813 unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits(); in expandRxSBG()
825 unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits(); in expandRxSBG()
839 unsigned BitSize = N.getValueType().getSizeInBits(); in expandRxSBG()
866 unsigned BitSize = N.getValueType().getSizeInBits(); in expandRxSBG()
909 if (!VT.isInteger() || VT.getSizeInBits() > 64) in tryRISBGZero()
984 if (!VT.isInteger() || VT.getSizeInBits() > 64) in tryRxSBG()
1061 if (Load->getMemoryVT().getSizeInBits() != in tryGather()
1062 Load->getValueType(0).getSizeInBits()) in tryGather()
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/external/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.cpp529 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) && in selectVSplatCommon()
530 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { in selectVSplatCommon()
605 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) && in selectVSplatUimmPow2()
606 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { in selectVSplatUimmPow2()
636 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) && in selectVSplatMaskL()
637 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { in selectVSplatMaskL()
670 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) && in selectVSplatMaskR()
671 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { in selectVSplatMaskR()
692 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) && in selectVSplatUimmInvPow2()
693 ImmValue.getBitWidth() == EltTy.getSizeInBits()) { in selectVSplatUimmInvPow2()
/external/llvm/test/CodeGen/Hexagon/vect/
Dvect-bitcast-1.ll3 ; Used to fail with: Assertion `VT.getSizeInBits() == Operand.getValueType().getSizeInBits() && "Ca…
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp930 O << ".param .b" << PtrVT.getSizeInBits() << " _"; in getPrototype()
982 sz = PtrVT.getSizeInBits(); in getPrototype()
1123 if (elemtype.getSizeInBits() < 16) { in LowerCall()
1161 if (EltVT.getSizeInBits() < 16) { in LowerCall()
1211 if (EltVT.getSizeInBits() == 64) in LowerCall()
1281 unsigned sz = VT.getSizeInBits(); in LowerCall()
1356 if (elemtype.getSizeInBits() < 16) { in LowerCall()
1492 unsigned sz = EltVT.getSizeInBits(); in LowerCall()
1558 if (EltVT.getSizeInBits() == 64) { in LowerCall()
1609 unsigned sz = VTs[i].getSizeInBits(); in LowerCall()
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/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp1576 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); in X86TargetLowering()
2020 switch (VT.getSizeInBits()) { in allowsMisalignedMemoryAccesses()
2584 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, in LowerMemArgument()
3341 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; in LowerCall()
3621 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; in MatchingStackOffset()
4251 unsigned ElSize = VT.getVectorElementType().getSizeInBits(); in isVEXTRACTIndex()
4269 unsigned ElSize = VT.getVectorElementType().getSizeInBits(); in isVINSERTIndex()
4302 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits(); in getExtractVEXTRACTImmediate()
4317 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits(); in getInsertVINSERTImmediate()
4439 unsigned Factor = VT.getSizeInBits()/vectorWidth; in ExtractSubVector()
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/external/llvm/lib/Target/XCore/
DXCoreSelectionDAGInfo.cpp26 unsigned SizeBitWidth = Size.getValueType().getSizeInBits(); in EmitTargetCodeForMemcpy()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp2082 int EltBits = EltVT.getSizeInBits(); in shouldExpandBuildVectorWithShuffles()
2212 unsigned Size = VT.getSizeInBits(); in LowerBUILD_VECTOR()
2310 SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), dl, MVT::i64); in LowerBUILD_VECTOR()
2323 if (VT.getSizeInBits() == 64 && in LowerBUILD_VECTOR()
2324 Operand.getValueType().getSizeInBits() == 32) { in LowerBUILD_VECTOR()
2334 if (VT.getSizeInBits() == 32) in LowerBUILD_VECTOR()
2353 unsigned Width = VecVT.getSizeInBits(); in LowerCONCAT_VECTORS()
2375 if (VT.getSizeInBits() != 32 && VT.getSizeInBits() != 64) in LowerCONCAT_VECTORS()
2389 if (VT.getSizeInBits() == 64 && OpN.getValueType().getSizeInBits() == 32) { in LowerCONCAT_VECTORS()
2396 if (VT.getSizeInBits() == 32) in LowerCONCAT_VECTORS()
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/external/llvm/lib/IR/
DValueTypes.cpp24 return getIntegerVT(Context, getSizeInBits()); in changeExtendedTypeToInteger()
29 EVT IntTy = getIntegerVT(Context, getVectorElementType().getSizeInBits()); in changeExtendedVectorElementTypeToInteger()
122 return "i" + utostr(getSizeInBits()); in getEVTString()
/external/llvm/include/llvm/IR/
DDataLayout.h484 uint64_t getSizeInBits() const { return 8 * StructSize; } in getSizeInBits() function
526 return getStructLayout(cast<StructType>(Ty))->getSizeInBits(); in getTypeSizeInBits()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp206 unsigned BitWidth = NextPowerOf2(VT.getSizeInBits() - 1); in getScalarShiftAmountTy()
212 assert(BitWidth >= Log2_32_Ceil(VT.getSizeInBits()) && in getScalarShiftAmountTy()
246 if (VT.getSizeInBits() <= 32) in getRegForInlineAsmConstraint()
248 if (VT.getSizeInBits() <= 64) in getRegForInlineAsmConstraint()

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