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Searched refs:hregClass (Results 1 – 19 of 19) sorted by relevance

/external/valgrind/VEX/priv/
Dhost_generic_reg_alloc2.c620 vreg_lrs[k].reg_class = hregClass(vreg); in doRegisterAllocation()
623 vassert(vreg_lrs[k].reg_class == hregClass(vreg)); in doRegisterAllocation()
1063 vassert(hregClass(univ->regs[j]) in doRegisterAllocation()
1064 == hregClass(rreg_state[j].vreg)); in doRegisterAllocation()
1107 vassert(hregClass(vregS) == hregClass(vregD)); in doRegisterAllocation()
1370 || hregClass(univ->regs[k]) != hregClass(vreg)) in doRegisterAllocation()
1437 if (hregClass(univ->regs[k]) != hregClass(vreg)) in doRegisterAllocation()
1463 ppHRegClass(hregClass(vreg)); in doRegisterAllocation()
1472 vassert(hregClass(univ->regs[spillee]) == hregClass(vreg)); in doRegisterAllocation()
Dhost_tilegx_isel.c184 vassert(hregClass(r_dst) == hregClass(r_src)); in mk_iMOVds_RR()
185 vassert(hregClass(r_src) == HRcInt32 || hregClass(r_src) == HRcInt64); in mk_iMOVds_RR()
384 return toBool(hregClass(am->GXam.IR.base) == HRcGPR() && in sane_AMode()
446 vassert(hregClass(r) == HRcGPR()); in iselWordExpr_R()
1133 vassert(hregClass(ri->GXrh.Reg.reg) == HRcGPR()); in iselWordExpr_RH()
1202 vassert(hregClass(ri->GXrh.Reg.reg) == HRcInt64); in iselWordExpr_RH6u()
Dhost_ppc_isel.c515 vassert(hregClass(r_dst) == hregClass(r_src)); in mk_iMOVds_RR()
516 vassert(hregClass(r_src) == HRcInt32 || in mk_iMOVds_RR()
517 hregClass(r_src) == HRcInt64); in mk_iMOVds_RR()
570 vassert(hregClass(r_srcHi) == HRcInt32); in mk_LoadRR32toFPR()
571 vassert(hregClass(r_srcLo) == HRcInt32); in mk_LoadRR32toFPR()
595 vassert(hregClass(r_src) == HRcInt64); in mk_LoadR64toFPR()
1113 vassert(hregClass(r_rmIR) == HRcGPR(env->mode64)); in roundModeIRtoPPC()
1343 vassert(hregClass(vSrc) == HRcVec128); in isNan()
1391 vassert(hregClass(r) == HRcGPR(env->mode64)); in iselWordExpr_R()
2507 return toBool( hregClass(am->Pam.IR.base) == HRcGPR(mode64) && in sane_AMode()
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Dhost_arm_defs.c151 switch (hregClass(reg)) { in ppHRegARM()
2564 rclass = hregClass(rreg); in genSpill_ARM()
2619 rclass = hregClass(rreg); in genReload_ARM()
2674 vassert(hregClass(r) == HRcInt32); in iregEnc()
2684 vassert(hregClass(r) == HRcFlt64); in dregEnc()
2694 vassert(hregClass(r) == HRcFlt32); in fregEnc()
2704 vassert(hregClass(r) == HRcVec128); in qregEnc()
3795 vassert(hregClass(i->ARMin.NLdStQ.dQ) == HRcVec128); in emit_ARMInstr()
3815 vassert(hregClass(i->ARMin.NLdStD.dD) == HRcFlt64); in emit_ARMInstr()
3844 regD = (hregClass(i->ARMin.NUnaryS.dst->reg) == HRcVec128) in emit_ARMInstr()
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Dhost_tilegx_defs.c79 vassert(hregClass(reg) == HRcInt32 || hregClass(reg) == HRcInt64 || in ppHRegTILEGX()
80 hregClass(reg) == HRcFlt32 || hregClass(reg) == HRcFlt64); in ppHRegTILEGX()
83 switch (hregClass(reg)) { in ppHRegTILEGX()
1210 switch (hregClass(rreg)) { in genSpill_TILEGX()
1218 ppHRegClass(hregClass(rreg)); in genSpill_TILEGX()
1230 switch (hregClass(rreg)) { in genReload_TILEGX()
1238 ppHRegClass(hregClass(rreg)); in genReload_TILEGX()
1342 vassert(hregClass(r) == HRcInt64); in iregNo()
Dhost_mips_isel.c328 vassert(hregClass(r_dst) == hregClass(r_src)); in mk_iMOVds_RR()
329 vassert(hregClass(r_src) == HRcInt32 || hregClass(r_src) == HRcInt64); in mk_iMOVds_RR()
360 vassert(hregClass(r_srcHi) == HRcInt32); in mk_LoadRR32toFPR()
361 vassert(hregClass(r_srcLo) == HRcInt32); in mk_LoadRR32toFPR()
692 return toBool(hregClass(am->Mam.IR.base) == HRcGPR(mode64) && in sane_AMode()
696 return toBool(hregClass(am->Mam.RR.base) == HRcGPR(mode64) && in sane_AMode()
698 hregClass(am->Mam.RR.index) == HRcGPR(mode64) && in sane_AMode()
788 vassert(hregClass(r) == HRcGPR(env->mode64)); in iselWordExpr_R()
1895 vassert(hregClass(ri->Mrh.Reg.reg) == HRcGPR(env->mode64)); in iselWordExpr_RH()
1965 vassert(hregClass(ri->Mrh.Reg.reg) == HRcInt32); in iselWordExpr_RH5u()
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Dhost_arm64_isel.c818 toBool( hregClass(am->ARM64am.RI9.reg) == HRcInt64 in sane_AMode()
826 toBool( hregClass(am->ARM64am.RI12.reg) == HRcInt64 in sane_AMode()
834 toBool( hregClass(am->ARM64am.RR.base) == HRcInt64 in sane_AMode()
836 && hregClass(am->ARM64am.RR.index) == HRcInt64 in sane_AMode()
929 vassert(hregClass(ri->ARM64riA.R.reg) == HRcInt64); in iselIntExpr_RIA()
1193 vassert(hregClass(ri->ARM64riL.R.reg) == HRcInt64); in iselIntExpr_RIL()
1252 vassert(hregClass(ri->ARM64ri6.R.reg) == HRcInt64); in iselIntExpr_RI6()
1437 vassert(hregClass(r) == HRcInt64); in iselIntExpr_R()
2076 vassert(hregClass(*rHi) == HRcInt64); in iselInt128Expr()
2078 vassert(hregClass(*rLo) == HRcInt64); in iselInt128Expr()
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Dhost_generic_regs.h149 static inline HRegClass hregClass ( HReg r ) in hregClass() function
Dhost_x86_isel.c291 vassert(hregClass(src) == HRcInt32); in mk_iMOVsd_RR()
292 vassert(hregClass(dst) == HRcInt32); in mk_iMOVsd_RR()
301 vassert(hregClass(src) == HRcVec128); in mk_vMOVsd_RR()
302 vassert(hregClass(dst) == HRcVec128); in mk_vMOVsd_RR()
845 vassert(hregClass(r) == HRcInt32); in iselIntExpr_R()
1535 toBool( hregClass(am->Xam.IR.reg) == HRcInt32 in sane_AMode()
1540 toBool( hregClass(am->Xam.IRRS.base) == HRcInt32 in sane_AMode()
1542 && hregClass(am->Xam.IRRS.index) == HRcInt32 in sane_AMode()
1632 vassert(hregClass(rmi->Xrmi.Reg.reg) == HRcInt32); in iselIntExpr_RMI()
1695 vassert(hregClass(ri->Xri.Reg.reg) == HRcInt32); in iselIntExpr_RI()
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Dhost_amd64_isel.c266 toBool( hregClass(am->Aam.IR.reg) == HRcInt64 in sane_AMode()
271 toBool( hregClass(am->Aam.IRRS.base) == HRcInt64 in sane_AMode()
273 && hregClass(am->Aam.IRRS.index) == HRcInt64 in sane_AMode()
312 vassert(hregClass(src) == HRcInt64); in mk_iMOVsd_RR()
313 vassert(hregClass(dst) == HRcInt64); in mk_iMOVsd_RR()
321 vassert(hregClass(src) == HRcVec128); in mk_vMOVsd_RR()
322 vassert(hregClass(dst) == HRcVec128); in mk_vMOVsd_RR()
906 vassert(hregClass(r) == HRcInt64); in iselIntExpr_R()
2034 vassert(hregClass(rmi->Armi.Reg.reg) == HRcInt64); in iselIntExpr_RMI()
2106 vassert(hregClass(ri->Ari.Reg.reg) == HRcInt64); in iselIntExpr_RI()
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Dhost_generic_regs.c73 switch (hregClass(r)) { in ppHReg()
Dhost_s390_isel.c1056 vassert(hregClass(*dst_hi) == HRcInt64); in s390_isel_int128_expr()
1057 vassert(hregClass(*dst_lo) == HRcInt64); in s390_isel_int128_expr()
1897 vassert(hregClass(dst) == HRcInt64); in s390_isel_int_expr()
2270 vassert(hregClass(*dst_hi) == HRcFlt64); in s390_isel_float128_expr()
2271 vassert(hregClass(*dst_lo) == HRcFlt64); in s390_isel_float128_expr()
2627 vassert(hregClass(dst) == HRcFlt64); in s390_isel_float_expr()
2965 vassert(hregClass(*dst_hi) == HRcFlt64); in s390_isel_dfp128_expr()
2966 vassert(hregClass(*dst_lo) == HRcFlt64); in s390_isel_dfp128_expr()
3287 vassert(hregClass(dst) == HRcFlt64); in s390_isel_dfp_expr()
Dhost_mips_defs.c162 vassert(hregClass(reg) == HRcInt32 || hregClass(reg) == HRcInt64 || in ppHRegMIPS()
163 hregClass(reg) == HRcFlt32 || hregClass(reg) == HRcFlt64); in ppHRegMIPS()
166 switch (hregClass(reg)) { in ppHRegMIPS()
1980 switch (hregClass(rreg)) { in genSpill_MIPS()
1997 ppHRegClass(hregClass(rreg)); in genSpill_MIPS()
2010 switch (hregClass(rreg)) { in genReload_MIPS()
2029 ppHRegClass(hregClass(rreg)); in genReload_MIPS()
2040 vassert(hregClass(r) == (mode64 ? HRcInt64 : HRcInt32)); in iregNo()
Dhost_arm_isel.c284 vassert(hregClass(src) == HRcInt32); in mk_iMOVds_RR()
285 vassert(hregClass(dst) == HRcInt32); in mk_iMOVds_RR()
740 toBool( hregClass(am->ARMam1.RI.reg) == HRcInt32 in sane_AMode1()
747 toBool( hregClass(am->ARMam1.RRS.base) == HRcInt32 in sane_AMode1()
749 && hregClass(am->ARMam1.RRS.index) == HRcInt32 in sane_AMode1()
809 toBool( hregClass(am->ARMam2.RI.reg) == HRcInt32 in sane_AMode2()
815 toBool( hregClass(am->ARMam2.RR.base) == HRcInt32 in sane_AMode2()
817 && hregClass(am->ARMam2.RR.index) == HRcInt32 in sane_AMode2()
872 return toBool( hregClass(am->reg) == HRcInt32 in sane_AModeV()
949 vassert(hregClass(ri->ARMri84.R.reg) == HRcInt32); in iselIntExpr_RI84()
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Dhost_x86_defs.c109 switch (hregClass(reg)) { in ppHRegX86()
829 vassert(hregClass(dst) == HRcVec128); in X86Instr_SseConst()
1714 switch (hregClass(rreg)) { in genSpill_X86()
1725 ppHRegClass(hregClass(rreg)); in genSpill_X86()
1739 switch (hregClass(rreg)) { in genReload_X86()
1750 ppHRegClass(hregClass(rreg)); in genReload_X86()
1837 vassert(hregClass(r) == HRcInt32); in iregEnc()
1847 vassert(hregClass(r) == HRcFlt64); in fregEnc()
1857 vassert(hregClass(r) == HRcVec128); in vregEnc()
Dhost_amd64_defs.c116 switch (hregClass(reg)) { in ppHRegAMD64()
145 switch (hregClass(reg)) { in ppHRegAMD64_lo32()
1963 switch (hregClass(rreg)) { in genSpill_AMD64()
1971 ppHRegClass(hregClass(rreg)); in genSpill_AMD64()
1985 switch (hregClass(rreg)) { in genReload_AMD64()
1993 ppHRegClass(hregClass(rreg)); in genReload_AMD64()
2005 vassert(hregClass(r) == HRcInt64); in iregEnc210()
2016 vassert(hregClass(r) == HRcInt64); in iregEnc3()
2027 vassert(hregClass(r) == HRcInt64); in iregEnc3210()
2038 vassert(hregClass(r) == HRcVec128); in vregEnc3210()
Dhost_arm64_defs.c153 switch (hregClass(reg)) { in ppHRegARM64()
877 vassert(hregClass(src) == HRcInt64); in ARM64Instr_MovI()
878 vassert(hregClass(dst) == HRcInt64); in ARM64Instr_MovI()
1335 vassert(hregClass(src) == HRcVec128); in ARM64Instr_VMov()
1336 vassert(hregClass(dst) == HRcVec128); in ARM64Instr_VMov()
1339 vassert(hregClass(src) == HRcFlt64); in ARM64Instr_VMov()
1340 vassert(hregClass(dst) == HRcFlt64); in ARM64Instr_VMov()
2512 rclass = hregClass(rreg); in genSpill_ARM64()
2553 rclass = hregClass(rreg); in genReload_ARM64()
2594 vassert(hregClass(r) == HRcInt64); in iregEnc()
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Dhost_ppc_defs.c167 switch (hregClass(reg)) { in ppHRegPPC()
448 vassert(hregClass(reg) == HRcVec128); in PPCVI5s_Reg()
3001 switch (hregClass(rreg)) { in genSpill_PPC()
3019 ppHRegClass(hregClass(rreg)); in genSpill_PPC()
3031 switch (hregClass(rreg)) { in genReload_PPC()
3048 ppHRegClass(hregClass(rreg)); in genReload_PPC()
3059 vassert(hregClass(r) == (mode64 ? HRcInt64 : HRcInt32)); in iregEnc()
3069 vassert(hregClass(fr) == HRcFlt64); in fregEnc()
3079 vassert(hregClass(v) == HRcVec128); in vregEnc()
5271 vassert(hregClass(i->Pin.AvSplat.src->Pvi.Reg) == HRcVec128); in emit_PPCInstr()
Dhost_s390_defs.c110 switch (hregClass(reg)) { in s390_hreg_as_string()
121 switch (hregClass(reg)) { in s390_hreg_as_string()
285 return hregIsVirtual(reg) && hregClass(reg) == HRcInt64; in is_virtual_gpr()
481 switch (hregClass(rreg)) { in genSpill_S390()
488 ppHRegClass(hregClass(rreg)); in genSpill_S390()
507 switch (hregClass(rreg)) { in genReload_S390()
514 ppHRegClass(hregClass(rreg)); in genReload_S390()
1203 hregClass(insn->variant.move.src) == hregClass(insn->variant.move.dst)) { in s390_insn_is_reg_reg_move()
7135 if (hregClass(insn->variant.load.dst) == HRcFlt64) { in s390_insn_load_emit()
7187 if (hregClass(insn->variant.store.src) == HRcFlt64) { in s390_insn_store_emit()
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