/external/valgrind/none/tests/mips64/ |
D | shift_instructions.stdout.exp-mips64 | 1 dsll $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000 2 dsll $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f 3 dsll $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f 4 dsll $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003 5 dsll $t0, $t1, 0x00 :: rt 0x12bd6aa, rs 0x12bd6aa, imm 0x0000 6 dsll $t2, $t3, 0x1f :: rt 0x95eb5500000000, rs 0x12bd6aa, imm 0x001f 7 dsll $a0, $a1, 0x0f :: rt 0x95eb550000, rs 0x12bd6aa, imm 0x000f 8 dsll $s0, $s1, 0x03 :: rt 0x95eb550, rs 0x12bd6aa, imm 0x0003 9 dsll $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000 10 dsll $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f [all …]
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D | shift_instructions.stdout.exp-mips64r2 | 1 drotr $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000 2 drotr $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f 3 drotr $a0, $a1, 0x0f :: rt 0x0, rs 0x0, imm 0x000f 4 drotr $s0, $s1, 0x03 :: rt 0x0, rs 0x0, imm 0x0003 5 drotr $t0, $t1, 0x00 :: rt 0x12bd6aa, rs 0x12bd6aa, imm 0x0000 6 drotr $t2, $t3, 0x1f :: rt 0x257ad5400000000, rs 0x12bd6aa, imm 0x001f 7 drotr $a0, $a1, 0x0f :: rt 0xad54000000000257, rs 0x12bd6aa, imm 0x000f 8 drotr $s0, $s1, 0x03 :: rt 0x4000000000257ad5, rs 0x12bd6aa, imm 0x0003 9 drotr $t0, $t1, 0x00 :: rt 0x0, rs 0x0, imm 0x0000 10 drotr $t2, $t3, 0x1f :: rt 0x0, rs 0x0, imm 0x001f [all …]
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D | logical_instructions.stdout.exp | 513 andi $t0, $t1, 0xff :: rt 0x0, rs 0x0, imm 0x00ff 514 andi $t2, $t3, 0xffff :: rt 0x0, rs 0x0, imm 0xffff 515 andi $a0, $a1, 0x0 :: rt 0x0, rs 0x0, imm 0x0000 516 andi $s0, $s1, 0x23 :: rt 0x0, rs 0x0, imm 0x0023 517 andi $t0, $t1, 0xff :: rt 0xaa, rs 0x12bd6aa, imm 0x00ff 518 andi $t2, $t3, 0xffff :: rt 0xd6aa, rs 0x12bd6aa, imm 0xffff 519 andi $a0, $a1, 0x0 :: rt 0x0, rs 0x12bd6aa, imm 0x0000 520 andi $s0, $s1, 0x23 :: rt 0x22, rs 0x12bd6aa, imm 0x0023 521 andi $t0, $t1, 0xff :: rt 0x0, rs 0x0, imm 0x00ff 522 andi $t2, $t3, 0xffff :: rt 0x0, rs 0x0, imm 0xffff [all …]
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D | arithmetic_instruction.stdout.exp-mips64r2 | 257 addi $t0, $t1, 0xff :: rt 0xff, rs 0x0, imm 0x00ff 258 addi $t2, $t3, 0xffff :: rt 0xffffffffffffffff, rs 0x0, imm 0xffff 259 addi $a0, $a1, 0x0 :: rt 0x0, rs 0x0, imm 0x0000 260 addi $s0, $s1, 0x23 :: rt 0x23, rs 0x0, imm 0x0023 261 addi $t0, $t1, 0xff :: rt 0xff, rs 0x0, imm 0x00ff 262 addi $t2, $t3, 0xffff :: rt 0xffffffffffffffff, rs 0x0, imm 0xffff 263 addi $a0, $a1, 0x0 :: rt 0x0, rs 0x0, imm 0x0000 264 addi $s0, $s1, 0x23 :: rt 0x23, rs 0x0, imm 0x0023 265 addi $t0, $t1, 0xff :: rt 0x9823c6d, rs 0x9823b6e, imm 0x00ff 266 addi $t2, $t3, 0xffff :: rt 0x9823b6d, rs 0x9823b6e, imm 0xffff [all …]
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D | arithmetic_instruction.stdout.exp-mips64 | 257 addi $t0, $t1, 0xff :: rt 0xff, rs 0x0, imm 0x00ff 258 addi $t2, $t3, 0xffff :: rt 0xffffffffffffffff, rs 0x0, imm 0xffff 259 addi $a0, $a1, 0x0 :: rt 0x0, rs 0x0, imm 0x0000 260 addi $s0, $s1, 0x23 :: rt 0x23, rs 0x0, imm 0x0023 261 addi $t0, $t1, 0xff :: rt 0xff, rs 0x0, imm 0x00ff 262 addi $t2, $t3, 0xffff :: rt 0xffffffffffffffff, rs 0x0, imm 0xffff 263 addi $a0, $a1, 0x0 :: rt 0x0, rs 0x0, imm 0x0000 264 addi $s0, $s1, 0x23 :: rt 0x23, rs 0x0, imm 0x0023 265 addi $t0, $t1, 0xff :: rt 0x9823c6d, rs 0x9823b6e, imm 0x00ff 266 addi $t2, $t3, 0xffff :: rt 0x9823b6d, rs 0x9823b6e, imm 0xffff [all …]
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/external/pcre/dist/sljit/ |
D | sljitNativePPC_64.c | 44 static sljit_si load_immediate(struct sljit_compiler *compiler, sljit_si reg, sljit_sw imm) in load_immediate() argument 51 if (imm <= SIMM_MAX && imm >= SIMM_MIN) in load_immediate() 52 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); in load_immediate() 54 if (!(imm & ~0xffff)) in load_immediate() 55 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); in load_immediate() 57 if (imm <= 0x7fffffffl && imm >= -0x80000000l) { in load_immediate() 58 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16))); in load_immediate() 59 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; in load_immediate() 63 tmp = (imm >= 0) ? imm : ~imm; in load_immediate() 67 tmp = (imm << shift); in load_immediate() [all …]
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D | sljitNativePPC_32.c | 29 static sljit_si load_immediate(struct sljit_compiler *compiler, sljit_si reg, sljit_sw imm) in load_immediate() argument 31 if (imm <= SIMM_MAX && imm >= SIMM_MIN) in load_immediate() 32 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); in load_immediate() 34 if (!(imm & ~0xffff)) in load_immediate() 35 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); in load_immediate() 37 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16))); in load_immediate() 38 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; in load_immediate() 101 return push_inst(compiler, ADDI | D(dst) | A(src1) | compiler->imm); in emit_single_op() 106 return push_inst(compiler, ADDIS | D(dst) | A(src1) | compiler->imm); in emit_single_op() 110 return push_inst(compiler, ADDIC | D(dst) | A(src1) | compiler->imm); in emit_single_op() [all …]
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D | sljitNativeARM_T2_32.c | 57 #define IMM3(imm) (imm << 6) argument 58 #define IMM8(imm) (imm) argument 76 #define IMM5(imm) \ argument 77 (COPY_BITS(imm, 2, 12, 3) | ((imm & 0x3) << 6)) 78 #define IMM12(imm) \ argument 79 (COPY_BITS(imm, 11, 26, 1) | COPY_BITS(imm, 8, 12, 3) | (imm & 0xff)) 206 …SLJIT_INLINE sljit_si emit_imm32_const(struct sljit_compiler *compiler, sljit_si dst, sljit_uw imm) in emit_imm32_const() argument 209 COPY_BITS(imm, 12, 16, 4) | COPY_BITS(imm, 11, 26, 1) | COPY_BITS(imm, 8, 12, 3) | (imm & 0xff))); in emit_imm32_const() 211 …COPY_BITS(imm, 12 + 16, 16, 4) | COPY_BITS(imm, 11 + 16, 26, 1) | COPY_BITS(imm, 8 + 16, 12, 3) | … in emit_imm32_const() 428 static sljit_uw get_imm(sljit_uw imm) in get_imm() argument [all …]
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D | sljitNativeARM_32.c | 384 static SLJIT_INLINE sljit_si emit_imm(struct sljit_compiler *compiler, sljit_si reg, sljit_sw imm) in emit_imm() argument 386 FAIL_IF(push_inst(compiler, MOVW | RD(reg) | ((imm << 4) & 0xf0000) | (imm & 0xfff))); in emit_imm() 387 return push_inst(compiler, MOVT | RD(reg) | ((imm >> 12) & 0xf0000) | ((imm >> 16) & 0xfff)); in emit_imm() 505 static sljit_uw get_imm(sljit_uw imm); 946 #define TYPE2_TRANSFER_IMM(imm) \ argument 947 (((imm) & 0xf) | (((imm) & 0xf0) << 4) | (1 << 22)) 1140 static sljit_uw get_imm(sljit_uw imm) in get_imm() argument 1144 if (imm <= 0xff) in get_imm() 1145 return SRC2_IMM | imm; in get_imm() 1147 if (!(imm & 0xff000000)) { in get_imm() [all …]
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/external/llvm/lib/Target/Sparc/ |
D | SparcInstrAliases.td | 66 // b<cond> $imm 67 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"), 68 (BCOND brtarget:$imm, condVal)>; 70 // b<cond>,a $imm 71 def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"), 72 (BCONDA brtarget:$imm, condVal)>; 74 // b<cond> %icc, $imm 75 def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"), 76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>; 78 // b<cond>,pt %icc, $imm [all …]
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D | Sparc.h | 117 inline static unsigned HI22(int64_t imm) { in HI22() argument 118 return (unsigned)((imm >> 10) & ((1 << 22)-1)); in HI22() 121 inline static unsigned LO10(int64_t imm) { in LO10() argument 122 return (unsigned)(imm & 0x3FF); in LO10() 125 inline static unsigned HIX22(int64_t imm) { in HIX22() argument 126 return HI22(~imm); in HIX22() 129 inline static unsigned LOX10(int64_t imm) { in LOX10() argument 130 return ~LO10(~imm); in LOX10()
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/external/llvm/lib/Target/AMDGPU/ |
D | SIIntrinsics.td | 28 llvm_i32_ty, // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW 31 llvm_i32_ty, // inst_offset(imm) 32 llvm_i32_ty, // dfmt(imm) 33 llvm_i32_ty, // nfmt(imm) 34 llvm_i32_ty, // offen(imm) 35 llvm_i32_ty, // idxen(imm) 36 llvm_i32_ty, // glc(imm) 37 llvm_i32_ty, // slc(imm) 38 llvm_i32_ty], // tfe(imm) 47 llvm_i32_ty, // inst_offset(imm) [all …]
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/external/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyInstrMemory.td | 52 def : Pat<(i32 (load (regPlusImm imm:$off, I32:$addr))), 53 (LOAD_I32 imm:$off, $addr)>; 54 def : Pat<(i64 (load (regPlusImm imm:$off, I32:$addr))), 55 (LOAD_I64 imm:$off, $addr)>; 56 def : Pat<(f32 (load (regPlusImm imm:$off, I32:$addr))), 57 (LOAD_F32 imm:$off, $addr)>; 58 def : Pat<(f64 (load (regPlusImm imm:$off, I32:$addr))), 59 (LOAD_F64 imm:$off, $addr)>; 78 def : Pat<(i32 (load imm:$off)), (LOAD_I32 imm:$off, (CONST_I32 0))>; 79 def : Pat<(i64 (load imm:$off)), (LOAD_I64 imm:$off, (CONST_I32 0))>; [all …]
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D | WebAssemblyInstrInfo.td | 117 def CONST_I32 : I<(outs I32:$res), (ins i32imm:$imm), 118 [(set I32:$res, imm:$imm)], 119 "i32.const\t$res, $imm">; 120 def CONST_I64 : I<(outs I64:$res), (ins i64imm:$imm), 121 [(set I64:$res, imm:$imm)], 122 "i64.const\t$res, $imm">; 123 def CONST_F32 : I<(outs F32:$res), (ins f32imm:$imm), 124 [(set F32:$res, fpimm:$imm)], 125 "f32.const\t$res, $imm">; 126 def CONST_F64 : I<(outs F64:$res), (ins f64imm:$imm), [all …]
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/external/clang/lib/Headers/ |
D | emmintrin.h | 839 #define _mm_slli_si128(a, imm) __extension__ ({ \ argument 842 ((imm)&0xF0) ? 0 : 16 - ((imm)&0xF), \ 843 ((imm)&0xF0) ? 0 : 17 - ((imm)&0xF), \ 844 ((imm)&0xF0) ? 0 : 18 - ((imm)&0xF), \ 845 ((imm)&0xF0) ? 0 : 19 - ((imm)&0xF), \ 846 ((imm)&0xF0) ? 0 : 20 - ((imm)&0xF), \ 847 ((imm)&0xF0) ? 0 : 21 - ((imm)&0xF), \ 848 ((imm)&0xF0) ? 0 : 22 - ((imm)&0xF), \ 849 ((imm)&0xF0) ? 0 : 23 - ((imm)&0xF), \ 850 ((imm)&0xF0) ? 0 : 24 - ((imm)&0xF), \ [all …]
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/external/v8/third_party/llvm-build/Release+Asserts/lib/clang/3.9.0/include/ |
D | emmintrin.h | 1079 #define _mm_slli_si128(a, imm) __extension__ ({ \ argument 1082 ((imm)&0xF0) ? 0 : 16 - ((imm)&0xF), \ 1083 ((imm)&0xF0) ? 0 : 17 - ((imm)&0xF), \ 1084 ((imm)&0xF0) ? 0 : 18 - ((imm)&0xF), \ 1085 ((imm)&0xF0) ? 0 : 19 - ((imm)&0xF), \ 1086 ((imm)&0xF0) ? 0 : 20 - ((imm)&0xF), \ 1087 ((imm)&0xF0) ? 0 : 21 - ((imm)&0xF), \ 1088 ((imm)&0xF0) ? 0 : 22 - ((imm)&0xF), \ 1089 ((imm)&0xF0) ? 0 : 23 - ((imm)&0xF), \ 1090 ((imm)&0xF0) ? 0 : 24 - ((imm)&0xF), \ [all …]
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/external/llvm/lib/Target/BPF/ |
D | BPFInstrInfo.td | 53 def i64immSExt32 : PatLeaf<(imm), 68 def BPF_CC_EQ : PatLeaf<(imm), 70 def BPF_CC_NE : PatLeaf<(imm), 72 def BPF_CC_GE : PatLeaf<(imm), 74 def BPF_CC_GT : PatLeaf<(imm), 76 def BPF_CC_GTU : PatLeaf<(imm), 78 def BPF_CC_GEU : PatLeaf<(imm), 104 : InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst), 105 !strconcat(OpcodeStr, "i\t$dst, $imm goto $BrDst"), 106 [(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> { [all …]
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonOperands.td | 122 def s32ImmPred : PatLeaf<(i32 imm), [{ 127 def s32_0ImmPred : PatLeaf<(i32 imm), [{ 132 def s31_1ImmPred : PatLeaf<(i32 imm), [{ 137 def s30_2ImmPred : PatLeaf<(i32 imm), [{ 142 def s29_3ImmPred : PatLeaf<(i32 imm), [{ 147 def s16ImmPred : PatLeaf<(i32 imm), [{ 152 def s11_0ImmPred : PatLeaf<(i32 imm), [{ 157 def s11_1ImmPred : PatLeaf<(i32 imm), [{ 162 def s11_2ImmPred : PatLeaf<(i32 imm), [{ 167 def s11_3ImmPred : PatLeaf<(i32 imm), [{ [all …]
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/external/llvm/lib/Target/Mips/ |
D | Mips64r6InstrInfo.td | 51 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm); 52 string AsmString = !strconcat(instr_asm, "\t$rt, $imm"); 137 def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f), 138 (OR64 (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)), 139 (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>, 141 def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f), 142 (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)), 143 (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>, 146 (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f), 148 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)), [all …]
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/external/mesa3d/src/gallium/auxiliary/rtasm/ |
D | rtasm_x86sse.c | 454 void x86_mov_reg_imm( struct x86_function *p, struct x86_reg dst, int imm ) in x86_mov_reg_imm() argument 456 DUMP_RI( dst, imm ); in x86_mov_reg_imm() 460 emit_1i(p, imm); in x86_mov_reg_imm() 463 void x86_mov_imm( struct x86_function *p, struct x86_reg dst, int imm ) in x86_mov_imm() argument 465 DUMP_RI( dst, imm ); in x86_mov_imm() 467 x86_mov_reg_imm(p, dst, imm); in x86_mov_imm() 472 emit_1i(p, imm); in x86_mov_imm() 476 void x86_mov16_imm( struct x86_function *p, struct x86_reg dst, uint16_t imm ) in x86_mov16_imm() argument 478 DUMP_RI( dst, imm ); in x86_mov16_imm() 483 emit_2ub(p, imm & 0xff, imm >> 8); in x86_mov16_imm() [all …]
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D | rtasm_x86sse.h | 202 void x86_mov_reg_imm( struct x86_function *p, struct x86_reg dst, int imm ); 203 void x86_add_imm( struct x86_function *p, struct x86_reg dst, int imm ); 204 void x86_or_imm( struct x86_function *p, struct x86_reg dst, int imm ); 205 void x86_and_imm( struct x86_function *p, struct x86_reg dst, int imm ); 206 void x86_sub_imm( struct x86_function *p, struct x86_reg dst, int imm ); 207 void x86_xor_imm( struct x86_function *p, struct x86_reg dst, int imm ); 208 void x86_cmp_imm( struct x86_function *p, struct x86_reg dst, int imm ); 255 void sse2_psllw_imm( struct x86_function *p, struct x86_reg dst, unsigned imm ); 256 void sse2_pslld_imm( struct x86_function *p, struct x86_reg dst, unsigned imm ); 257 void sse2_psllq_imm( struct x86_function *p, struct x86_reg dst, unsigned imm ); [all …]
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/external/vixl/src/vixl/a64/ |
D | macro-assembler-a64.cc | 361 uint64_t imm) { in MoveImmediateHelper() argument 363 VIXL_ASSERT(is_uint32(imm) || is_int32(imm) || rd.Is64Bits()); in MoveImmediateHelper() 386 if (OneInstrMoveImmediateHelper(masm, rd, imm)) { in MoveImmediateHelper() 401 if (CountClearHalfWords(~imm, reg_size) > in MoveImmediateHelper() 402 CountClearHalfWords(imm, reg_size)) { in MoveImmediateHelper() 421 uint64_t imm16 = (imm >> (16 * i)) & 0xffff; in MoveImmediateHelper() 455 int64_t imm) { in OneInstrMoveImmediateHelper() argument 460 if (IsImmMovz(imm, reg_size) && !dst.IsSP()) { in OneInstrMoveImmediateHelper() 464 masm->movz(dst, imm); in OneInstrMoveImmediateHelper() 467 } else if (IsImmMovn(imm, reg_size) && !dst.IsSP()) { in OneInstrMoveImmediateHelper() [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 45 def t2_so_reg : Operand<i32>, // reg imm 56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ 62 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ 70 def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{ 94 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{ 102 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{ 113 def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 129 def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{ 135 def imm1_255_neg : PatLeaf<(i32 imm), [{ 140 def imm0_255_not : PatLeaf<(i32 imm), [{ [all …]
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/external/valgrind/VEX/priv/ |
D | guest_tilegx_toIR.c | 242 static IRStmt* dis_branch ( IRExpr* guard, ULong imm ) in dis_branch() argument 249 IRConst_U64(imm), OFFB_PC); in dis_branch() 294 ULong cins, opcode = -1, rd, ra, rb, imm = 0; in disInstr_TILEGX_WRK() local 451 imm = decoded[n].operand_values[opi]; in disInstr_TILEGX_WRK() 492 assign(t2, mkU64(extend_s_8to64(imm))); in disInstr_TILEGX_WRK() 497 assign(t2, mkU64(extend_s_16to64(imm))); in disInstr_TILEGX_WRK() 542 mkU64(extend_s_8to64(imm)))); in disInstr_TILEGX_WRK() 548 mkU64(extend_s_16to64(imm)))); in disInstr_TILEGX_WRK() 563 mkU32(imm)), 32)); in disInstr_TILEGX_WRK() 570 mkU32(imm)), 32)); in disInstr_TILEGX_WRK() [all …]
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
D | brw_eu.h | 391 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F); in brw_imm_f() local 392 imm.dw1.f = f; in brw_imm_f() 393 return imm; in brw_imm_f() 399 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D); in brw_imm_d() local 400 imm.dw1.d = d; in brw_imm_d() 401 return imm; in brw_imm_d() 407 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD); in brw_imm_ud() local 408 imm.dw1.ud = ud; in brw_imm_ud() 409 return imm; in brw_imm_ud() 415 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW); in brw_imm_uw() local [all …]
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