| /external/ltrace/sysdeps/linux-gnu/arm/ |
| D | trace.c | 445 const unsigned imm2 = BITS(inst2, 0, 10); in thumb_get_next_pcs() local
450 = ((imm1 << 12) + (imm2 << 1)); in thumb_get_next_pcs()
477 const unsigned imm2 = BITS(inst2, 0, 10); in thumb_get_next_pcs() local
483 offset += (imm1 << 12) + (imm2 << 1); in thumb_get_next_pcs()
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| /external/v8/src/arm64/ |
| D | assembler-arm64-inl.h | 1166 Instr Assembler::ImmBarrierDomain(int imm2) {
1167 DCHECK(is_uint2(imm2));
1168 return imm2 << ImmBarrierDomain_offset;
1172 Instr Assembler::ImmBarrierType(int imm2) {
1173 DCHECK(is_uint2(imm2));
1174 return imm2 << ImmBarrierType_offset;
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| D | assembler-arm64.h | 1793 inline static Instr ImmBarrierDomain(int imm2);
1794 inline static Instr ImmBarrierType(int imm2);
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| /external/v8/src/wasm/ |
| D | encoder.cc | 105 const byte imm2) { in EmitWithU8U8() argument
108 body_.push_back(imm2); in EmitWithU8U8()
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| D | encoder.h | 139 void EmitWithU8U8(WasmOpcode opcode, const byte imm1, const byte imm2);
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| /external/llvm/lib/Target/Mips/ |
| D | Mips32r6InstrFormats.td | 493 bits<2> imm2;
502 let Inst{7-6} = imm2;
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| D | MicroMips32r6InstrFormats.td | 367 bits<2> imm2;
375 let Inst{10-9} = imm2;
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| D | Mips32r6InstrInfo.td | 595 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
596 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2");
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| D | MicroMips32r6InstrInfo.td | 461 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
462 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
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| D | MipsFastISel.cpp | 175 uint64_t imm2, unsigned Op3, bool Op3IsKill) { in fastEmitInst_riir() argument
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| /external/valgrind/none/tests/ppc32/ |
| D | test_dfp5.c | 239 typedef void (*test_funcp_t)(unsigned int imm, unsigned int imm2, dfp_val_t *valB);
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| /external/valgrind/none/tests/ppc64/ |
| D | test_dfp5.c | 239 typedef void (*test_funcp_t)(unsigned int imm, unsigned int imm2, dfp_val_t *valB);
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| /external/pcre/dist/sljit/ |
| D | sljitNativeARM_32.c | 1182 sljit_uw imm2; in generate_int() local
1225 imm2 = SRC2_IMM | ((imm >> 8) & 0xff) | (((rol + 8) & 0xf) << 8); in generate_int()
1248 imm2 = SRC2_IMM | (imm >> 24) | ((rol & 0xf) << 8); in generate_int()
1278 imm2 = SRC2_IMM | (imm >> 24) | ((rol & 0xf) << 8); in generate_int()
1284 FAIL_IF(push_inst(compiler, EMIT_DATA_PROCESS_INS(positive ? ORR_DP : BIC_DP, 0, reg, reg, imm2))); in generate_int()
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| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.h | 4027 static Instr ImmBarrierDomain(int imm2) { in ImmBarrierDomain() argument
4028 VIXL_ASSERT(is_uint2(imm2)); in ImmBarrierDomain()
4029 return imm2 << ImmBarrierDomain_offset; in ImmBarrierDomain()
4032 static Instr ImmBarrierType(int imm2) { in ImmBarrierType() argument
4033 VIXL_ASSERT(is_uint2(imm2)); in ImmBarrierType()
4034 return imm2 << ImmBarrierType_offset; in ImmBarrierType()
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| /external/vixl/test/ |
| D | test-simulator-a64.cc | 175 const VRegister& vd, int imm1, const VRegister& vn, int imm2);
2405 for (unsigned imm2 = 0; imm2 < inputs_imm2_length; imm2++) { in TestOpImmOpImmNEON() local
2415 (imm2 * vd_lane_count) + lane; in TestOpImmOpImmNEON()
2437 (imm2 * vd_lane_count) + lane; in TestOpImmOpImmNEON()
2441 unsigned input_index_imm2 = imm2; in TestOpImmOpImmNEON()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 265 // t2addrmode_so_reg := reg + (reg << imm2)
602 let Inst{7-6} = 0b00; // imm2
686 let Inst{7-6} = 0b00; // imm2
807 let Inst{7-6} = 0b00; // imm2
849 let Inst{7-6} = 0b00; // imm2
947 let Inst{7-6} = 0b00; // imm2
1672 let Inst{5-4} = addr{1-0}; // imm2
2267 let Inst{7-6} = 0b00; // imm2 = '00'
2290 let Inst{7-6} = 0b00; // imm2 = '00'
2500 let Inst{7-6} = 0b00; // imm2
[all …]
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1793 MCOperand imm2(MCOperand::createExpr( in processInstruction() local
1795 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2); in processInstruction()
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| /external/valgrind/VEX/priv/ |
| D | host_ppc_defs.c | 3138 UInt imm1, UInt imm2, UInt opc2, in mkFormMD() argument
3146 vassert(imm2 < 0x40); in mkFormMD()
3148 imm2 = ((imm2 & 0x1F) << 1) | (imm2 >> 5); in mkFormMD()
3150 ((imm1 & 0x1F)<<11) | (imm2<<5) | in mkFormMD()
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| D | guest_arm_toIR.c | 20316 UInt imm2 = INSN1(5,4); in disInstr_THUMB_WRK() local
20353 binop(Iop_Shl32, getIRegT(rM), mkU8(imm2)) )); in disInstr_THUMB_WRK()
20423 nm, rT, rN, rM, imm2); in disInstr_THUMB_WRK()
21611 UInt imm2 = INSN1(5,4); in disInstr_THUMB_WRK() local
21613 DIP("pld%s [r%u, r%u, lsl %u]\n", bW ? "w" : "", rN, rM, imm2); in disInstr_THUMB_WRK()
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_peephole.cpp | 552 const int s, ImmediateValue& imm2) in tryCollapseChainedMULs() argument
558 float f = imm2.reg.data.f32; in tryCollapseChainedMULs()
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| /external/llvm/lib/Target/X86/ |
| D | README-SSE.txt | 467 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXIntrinsics.td | 920 def imm2 : NVPTXInst<(outs regclass:$dst),
|