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Searched refs:imm3 (Results 1 – 13 of 13) sorted by relevance

/external/lldb/source/Plugins/Process/Utility/
DARMUtils.h321 const uint32_t imm3 = bits(opcode, 14, 12); in ThumbExpandImm_C() local
323 const uint32_t imm12 = i << 11 | imm3 << 8 | abcdefgh; in ThumbExpandImm_C()
368 const uint32_t imm3 = bits(opcode, 14, 12); in ThumbImm12() local
370 const uint32_t imm12 = i << 11 | imm3 << 8 | imm8; in ThumbImm12()
/external/v8/src/arm/
Ddisasm-arm.cc1778 int imm3 = instr->Bits(21, 19); in DecodeSpecialCondition() local
1780 "vmovl.s%d q%d, d%d", imm3*8, Vd, Vm); in DecodeSpecialCondition()
1792 int imm3 = instr->Bits(21, 19); in DecodeSpecialCondition() local
1794 "vmovl.u%d q%d, d%d", imm3*8, Vd, Vm); in DecodeSpecialCondition()
Dsimulator-arm.cc3826 int imm3 = instr->Bits(21, 19); in DecodeSpecialCondition() local
3827 if ((imm3 != 1) && (imm3 != 2) && (imm3 != 4)) UNIMPLEMENTED(); in DecodeSpecialCondition()
3828 int esize = 8 * imm3; in DecodeSpecialCondition()
3850 int imm3 = instr->Bits(21, 19); in DecodeSpecialCondition() local
3851 if ((imm3 != 1) && (imm3 != 2) && (imm3 != 4)) UNIMPLEMENTED(); in DecodeSpecialCondition()
3852 int esize = 8 * imm3; in DecodeSpecialCondition()
/external/llvm/lib/Target/ARM/
DARMInstrThumb.td880 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
882 "add", "\t$Rd, $Rm, $imm3",
883 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
885 bits<3> imm3;
886 let Inst{8-6} = imm3;
1167 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1169 "sub", "\t$Rd, $Rm, $imm3",
1170 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1172 bits<3> imm3;
1173 let Inst{8-6} = imm3;
DARMInstrThumb2.td601 let Inst{14-12} = 0b000; // imm3
685 let Inst{14-12} = 0b000; // imm3
806 let Inst{14-12} = 0b000; // imm3
848 let Inst{14-12} = 0b000; // imm3
945 let Inst{14-12} = 0b000; // imm3
2266 let Inst{14-12} = 0b000; // imm3 = '000'
2289 let Inst{14-12} = 0b000; // imm3 = '000'
2499 let Inst{14-12} = 0b000; // imm3
3117 let Inst{14-12} = 0b000; // imm3
/external/vixl/src/vixl/a64/
Dassembler-a64.h4017 static Instr ImmSysOp1(int imm3) { in ImmSysOp1() argument
4018 VIXL_ASSERT(is_uint3(imm3)); in ImmSysOp1()
4019 return imm3 << SysOp1_offset; in ImmSysOp1()
4022 static Instr ImmSysOp2(int imm3) { in ImmSysOp2() argument
4023 VIXL_ASSERT(is_uint3(imm3)); in ImmSysOp2()
4024 return imm3 << SysOp2_offset; in ImmSysOp2()
/external/llvm/lib/Target/Mips/
DMips16InstrFormats.td529 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
/external/lldb/source/Plugins/Instruction/ARM/
DEmulateInstructionARM.cpp853 uint32_t imm3 = Bits32 (opcode, 14, 12); in EmulateMOVRdImm() local
856 imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8; in EmulateMOVRdImm()
2516 uint32_t imm3 = Bits32 (opcode, 14, 12); in EmulateADDImmThumb() local
2518 imm32 = (i << 11) | (imm3 << 8) | imm8; in EmulateADDImmThumb()
/external/valgrind/VEX/priv/
Dhost_arm_defs.c4535 UInt imm3 = (imm >> 4) & 0x7; in emit_ARMInstr() local
4570 insn = XXXXXXXX(0xF, BITS4(0,0,1,j), BITS4(1,D,0,0), imm3, regD, in emit_ARMInstr()
Dguest_arm_toIR.c2569 UInt imm1, UInt imm3, UInt imm8 ) in thumbExpandImm() argument
2572 vassert(imm3 < (1<<3)); in thumbExpandImm()
2574 UInt i_imm3_a = (imm1 << 4) | (imm3 << 1) | ((imm8 >> 7) & 1); in thumbExpandImm()
2607 UInt imm3 = SLICE_UInt(i1,14,12); in thumbExpandImm_from_I0_I1() local
2609 return thumbExpandImm(updatesC, imm1, imm3, imm8); in thumbExpandImm_from_I0_I1()
Dguest_arm64_toIR.c3101 UInt imm3 = INSN(12,10); in dis_ARM64_data_processing_register() local
3148 assign(argR, binop(Iop_Shl64, xMw, mkU8(imm3))); in dis_ARM64_data_processing_register()
3175 nameExt[opt], imm3); in dis_ARM64_data_processing_register()
/external/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td929 def imm3 : NVPTXInst<(outs regclass:$dst),
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td689 // {2-0} - imm3