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Searched refs:isBeforeLegalizeOps (Results 1 – 9 of 9) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp1282 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
1488 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
1546 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
1636 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
1651 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
1886 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
2017 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
2028 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp473 if (DCI.isBeforeLegalizeOps()) in performDivRemCombine()
583 if (DCI.isBeforeLegalizeOps()) in performSELECTCombine()
662 if (DCI.isBeforeLegalizeOps()) in performCMovFPCombine()
692 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performANDCombine()
735 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performORCombine()
789 if (DCI.isBeforeLegalizeOps()) in performADDCombine()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp7369 if (DCI.isBeforeLegalizeOps()) in performXorCombine()
7420 if (DCI.isBeforeLegalizeOps()) in performMulCombine()
7828 if (DCI.isBeforeLegalizeOps()) in performBitcastCombine()
7931 if (DCI.isBeforeLegalizeOps()) in performConcatVectorsCombine()
7975 if (DCI.isBeforeLegalizeOps()) in tryCombineFixedPointConvert()
8217 if (DCI.isBeforeLegalizeOps()) in performAddSubLongCombine()
8266 if (DCI.isBeforeLegalizeOps()) in tryCombineLongOpWithDup()
8441 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND && in performExtendCombine()
8480 if (!DCI.isBeforeLegalizeOps()) in performExtendCombine()
8663 if (DCI.isBeforeLegalizeOps()) in performPostLD1Combine()
[all …]
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1636 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
1653 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
/external/llvm/include/llvm/Target/
DTargetLowering.h2183 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; } in isBeforeLegalizeOps() function
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1988 if (DCI.isBeforeLegalizeOps() || in PerformDAGCombine()
DSIISelLowering.cpp2018 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
DAMDGPUISelLowering.cpp2564 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp23552 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() && in PerformShuffleCombine()
23629 if (DCI.isBeforeLegalizeOps()) in XFormVExtractWithShuffleIntoLoad()
24395 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && in PerformSELECTCombine()
24433 DCI.isBeforeLegalizeOps()); in PerformSELECTCombine()
24795 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { in PerformCMOVCombine()
25457 if (DCI.isBeforeLegalizeOps()) in PerformAndCombine()
25523 if (DCI.isBeforeLegalizeOps()) in PerformOrCombine()
25764 if (DCI.isBeforeLegalizeOps()) in PerformXorCombine()
25916 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() && in PerformLOADCombine()
26899 !DCI.isBeforeLegalizeOps()); in PerformBTCombine()
[all …]