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Searched refs:isInConsecutiveRegs (Results 1 – 5 of 5) sorted by relevance

/external/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp354 if (Out.Flags.isInConsecutiveRegs()) in LowerCall()
432 if (In.Flags.isInConsecutiveRegs()) in LowerCall()
489 if (Out.Flags.isInConsecutiveRegs()) in LowerReturn()
518 if (In.Flags.isInConsecutiveRegs()) in LowerFormalArguments()
/external/llvm/include/llvm/Target/
DTargetCallingConv.h88 bool isInConsecutiveRegs() const { return Flags & InConsecutiveRegs; } in isInConsecutiveRegs() function
DTargetCallingConv.td47 class CCIfConsecutiveRegs<CCAction A> : CCIf<"ArgFlags.isInConsecutiveRegs()", A> {
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp2648 if (!Flags.isInConsecutiveRegs()) in CalculateStackSlotSize()
2685 if (Flags.isInConsecutiveRegs()) { in CalculateStackSlotAlignment()
3334 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize; in LowerFormalArguments_64SVR4()
5140 } else if (!Flags.isInConsecutiveRegs()) { in LowerCall_64SVR4()
5176 !isLittleEndian && !Flags.isInConsecutiveRegs()) { in LowerCall_64SVR4()
5192 Flags.isInConsecutiveRegs()) ? 4 : 8; in LowerCall_64SVR4()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp2485 !Ins[i].Flags.isInConsecutiveRegs()) in LowerFormalArguments()
3048 !Flags.isInConsecutiveRegs()) { in LowerCall()