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Searched refs:opc1 (Results 1 – 13 of 13) sorted by relevance

/external/valgrind/VEX/priv/
Dhost_ppc_defs.c3125 static UChar* mkFormD ( UChar* p, UInt opc1, in mkFormD() argument
3129 vassert(opc1 < 0x40); in mkFormD()
3133 theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | (imm)); in mkFormD()
3137 static UChar* mkFormMD ( UChar* p, UInt opc1, UInt r1, UInt r2, in mkFormMD() argument
3142 vassert(opc1 < 0x40); in mkFormMD()
3149 theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | in mkFormMD()
3155 static UChar* mkFormX ( UChar* p, UInt opc1, UInt r1, UInt r2, in mkFormX() argument
3159 vassert(opc1 < 0x40); in mkFormX()
3165 theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | in mkFormX()
3170 static UChar* mkFormXO ( UChar* p, UInt opc1, UInt r1, UInt r2, in mkFormXO() argument
[all …]
Dguest_ppc_toIR.c3475 UChar opc1 = ifieldOPC(theInstr); in dis_int_arith() local
3495 switch (opc1) { in dis_int_arith()
4112 UChar opc1 = ifieldOPC(theInstr); in dis_int_cmp() local
4136 switch (opc1) { in dis_int_cmp()
4232 UChar opc1 = ifieldOPC(theInstr); in dis_int_logic() local
4250 switch (opc1) { in dis_int_logic()
4610 UChar opc1 = ifieldOPC(theInstr); in dis_int_parity() local
4640 if (opc1 != 0x1f || rB_addr || b0) { in dis_int_parity()
4739 UChar opc1 = ifieldOPC(theInstr); in dis_int_rot() local
4763 switch (opc1) { in dis_int_rot()
[all …]
Dhost_tilegx_defs.c1349 static UChar *doAMode_IR ( UChar * p, UInt opc1, UInt rSD, TILEGXAMode * am ) in doAMode_IR() argument
1356 if (opc1 == TILEGX_OPC_ST1 || opc1 == TILEGX_OPC_ST2 || in doAMode_IR()
1357 opc1 == TILEGX_OPC_ST4 || opc1 == TILEGX_OPC_ST) { in doAMode_IR()
1363 p = mkInsnBin(p, mkTileGxInsn(opc1, 2, 51, rSD)); in doAMode_IR()
1366 p = mkInsnBin(p, mkTileGxInsn(opc1, 2, rA, rSD)); in doAMode_IR()
1374 p = mkInsnBin(p, mkTileGxInsn(opc1, 2, rSD, 51)); in doAMode_IR()
1377 p = mkInsnBin(p, mkTileGxInsn(opc1, 2, rSD, rA)); in doAMode_IR()
Dhost_mips_defs.c2152 static UChar *mkFormS(UChar * p, UInt opc1, UInt rRD, UInt rRS, UInt rRT, in mkFormS() argument
2156 vassert(opc1 <= 0x3F); in mkFormS()
2163 theInstr = ((opc1 << 26) | (rRS << 21) | (rRT << 16) | (rRD << 11) | in mkFormS()
2169 static UChar *doAMode_IR(UChar * p, UInt opc1, UInt rSD, MIPSAMode * am, in doAMode_IR() argument
2184 if (opc1 < 40) { in doAMode_IR()
2194 p = mkFormI(p, opc1, rA, r_dst, idx); in doAMode_IR()
2196 if (opc1 >= 40) { in doAMode_IR()
2209 static UChar *doAMode_RR(UChar * p, UInt opc1, UInt rSD, MIPSAMode * am, in doAMode_RR() argument
2223 if (opc1 < 40) { in doAMode_RR()
2238 p = mkFormI(p, opc1, rA, r_dst, 0); in doAMode_RR()
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Dhost_arm_defs.c3835 UInt opc, opc1, opc2; in emit_ARMInstr() local
3888 opc1 = (opc >> 2) & 3; in emit_ARMInstr()
3890 insn = XXXXXXXX(0xE, X1110, BITS4(0,(opc1 >> 1),(opc1 & 1),0), in emit_ARMInstr()
3929 opc1 = (opc >> 2) & 3; in emit_ARMInstr()
3931 insn = XXXXXXXX(0xE, X1110, BITS4(1,(opc1 >> 1),(opc1 & 1),1), in emit_ARMInstr()
3977 opc1 = (opc >> 2) & 3; in emit_ARMInstr()
3979 insn = XXXXXXXX(0xE, X1110, BITS4(0,(opc1 >> 1),(opc1 & 1),1), in emit_ARMInstr()
Dguest_mips_toIR.c2071 UChar opc1 = get_opcode(theInstr); in dis_instr_branch() local
2099 switch (opc1) { in dis_instr_branch()
2238 UChar opc1 = get_opcode(theInstr); in dis_instr_CVM() local
2256 switch(opc1) { in dis_instr_CVM()
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td4788 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4790 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4791 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4794 bits<4> opc1;
4807 let Inst{23-20} = opc1;
4810 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4812 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4813 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4817 bits<4> opc1;
4830 let Inst{23-20} = opc1;
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DARMInstrThumb2.td4126 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4134 bits<3> opc1;
4141 let Inst{23-21} = opc1;
4149 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4157 bits<4> opc1;
4163 let Inst{7-4} = opc1;
4170 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4172 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4175 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4176 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
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/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.td221 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
222 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
230 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
231 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
237 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
239 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
258 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
260 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
269 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
271 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td5174 class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1,
5178 "$Rx "#opc2#opc1#"($Rs, #$u5)",
5204 class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1,
5208 "$Rx "#opc2#opc1#"($Rs, $Rt)",
5231 class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1,
5235 "$Rxx "#opc2#opc1#"($Rss, #$u6)",
5261 class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1,
5265 "$Rxx "#opc2#opc1#"($Rss, $Rt)",
5296 multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5298 defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>;
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/external/llvm/lib/Target/X86/
DX86InstrControl.td85 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
86 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm,
DX86InstrAVX512.td2435 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2437 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2440 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp5202 unsigned opc1 = fieldFromInstruction(Val, 4, 4); in DecodeMRRC2() local
5214 Inst.addOperand(MCOperand::createImm(opc1)); in DecodeMRRC2()