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/external/libvpx/libvpx/vpx_dsp/mips/
Didct32x32_msa.c44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
58 DOTP_CONST_PAIR(reg0, reg4, cospi_16_64, cospi_16_64, reg0, reg4); in idct32x8_row_even_process_store()
60 BUTTERFLY_4(reg4, reg0, reg2, reg6, vec1, vec3, vec2, vec0); in idct32x8_row_even_process_store()
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
66 DOTP_CONST_PAIR(reg0, reg7, cospi_30_64, cospi_2_64, reg0, reg7); in idct32x8_row_even_process_store()
71 vec0 = reg0 + reg4; in idct32x8_row_even_process_store()
72 reg0 = reg0 - reg4; in idct32x8_row_even_process_store()
87 DOTP_CONST_PAIR(reg7, reg0, cospi_24_64, cospi_8_64, reg0, reg7); in idct32x8_row_even_process_store()
90 vec0 = reg0 - reg6; in idct32x8_row_even_process_store()
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Didct16x16_msa.c15 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_rows_msa() local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vpx_idct16_1d_rows_msa()
24 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
31 DOTP_CONST_PAIR(reg0, reg8, cospi_16_64, cospi_16_64, reg0, reg8); in vpx_idct16_1d_rows_msa()
33 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vpx_idct16_1d_rows_msa()
34 SUB4(reg2, loc1, reg14, loc0, reg6, loc3, reg10, loc2, reg0, reg12, reg4, in vpx_idct16_1d_rows_msa()
59 loc0 = reg0 + loc1; in vpx_idct16_1d_rows_msa()
60 loc1 = reg0 - loc1; in vpx_idct16_1d_rows_msa()
63 reg0 = loc2; in vpx_idct16_1d_rows_msa()
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Dtxfm_macros_msa.h16 #define DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) { \ argument
23 ILVRL_H2_SW((-reg1), reg0, s1_m, s0_m); \
24 ILVRL_H2_SW(reg0, reg1, s3_m, s2_m); \
/external/llvm/test/CodeGen/X86/
D2010-05-12-FastAllocKills.ll9 ; %reg1025<def> = MUL_Fp80m32 %reg1024, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
18 ; %FP0<def> = LD_Fp80m <fi#3>, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
20 ; %FP2<def> = MUL_Fp80m32 %FP1, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
22 ; ST_FpP80m <fi#3>, 1, %reg0, 0, %reg0, %FP0<kill>; mem:ST10[FixedStack3](align=4)
23 ; ST_FpP80m <fi#4>, 1, %reg0, 0, %reg0, %FP1<kill>; mem:ST10[FixedStack4](align=4)
24 ; ST_FpP80m <fi#5>, 1, %reg0, 0, %reg0, %FP2<kill>; mem:ST10[FixedStack5](align=4)
/external/llvm/test/CodeGen/ARM/
D2011-11-29-128bitArithmetics.ll32 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
33 ; CHECK: movt [[reg0]], :upper16:{{.*}}
63 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
64 ; CHECK: movt [[reg0]], :upper16:{{.*}}
94 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
95 ; CHECK: movt [[reg0]], :upper16:{{.*}}
125 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
126 ; CHECK: movt [[reg0]], :upper16:{{.*}}
156 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
157 ; CHECK: movt [[reg0]], :upper16:{{.*}}
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Dfast-isel-pic.ll11 ; THUMB: movw [[reg0:r[0-9]+]],
12 ; THUMB: movt [[reg0]],
13 ; THUMB: add [[reg0]], pc
15 ; THUMB-ELF: ldr r[[reg0:[0-9]+]],
16 ; THUMB-ELF: add r[[reg0]], pc
17 ; THUMB-ELF: ldr r[[reg0]], [r[[reg0]]]
/external/llvm/test/CodeGen/AMDGPU/
Dtex-clause-antidep.ll6 define void @test(<4 x float> inreg %reg0) #0 {
7 %1 = extractelement <4 x float> %reg0, i32 0
8 %2 = extractelement <4 x float> %reg0, i32 1
9 %3 = extractelement <4 x float> %reg0, i32 2
10 %4 = extractelement <4 x float> %reg0, i32 3
Dfmad.ll5 define void @test(<4 x float> inreg %reg0) #0 {
6 %r0 = extractelement <4 x float> %reg0, i32 0
7 %r1 = extractelement <4 x float> %reg0, i32 1
8 %r2 = extractelement <4 x float> %reg0, i32 2
Dtexture-input-merge.ll5 define void @test(<4 x float> inreg %reg0) #0 {
6 %1 = extractelement <4 x float> %reg0, i32 0
7 %2 = extractelement <4 x float> %reg0, i32 1
8 %3 = extractelement <4 x float> %reg0, i32 2
9 %4 = extractelement <4 x float> %reg0, i32 3
Dllvm.pow.ll8 define void @test1(<4 x float> inreg %reg0) #0 {
9 %r0 = extractelement <4 x float> %reg0, i32 0
10 %r1 = extractelement <4 x float> %reg0, i32 1
30 define void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
31 %vec = call <4 x float> @llvm.pow.v4f32( <4 x float> %reg0, <4 x float> %reg1)
Dfmin.ll5 define void @test(<4 x float> inreg %reg0) #0 {
6 %r0 = extractelement <4 x float> %reg0, i32 0
7 %r1 = extractelement <4 x float> %reg0, i32 1
Dfmax.ll5 define void @test(<4 x float> inreg %reg0) #0 {
6 %r0 = extractelement <4 x float> %reg0, i32 0
7 %r1 = extractelement <4 x float> %reg0, i32 1
Dllvm.AMDGPU.mul.ll5 define void @test(<4 x float> inreg %reg0) #0 {
6 %r0 = extractelement <4 x float> %reg0, i32 0
7 %r1 = extractelement <4 x float> %reg0, i32 1
Dr600-encoding.ll13 define void @test(<4 x float> inreg %reg0) #0 {
15 %r0 = extractelement <4 x float> %reg0, i32 0
16 %r1 = extractelement <4 x float> %reg0, i32 1
Dreciprocal.ll5 define void @test(<4 x float> inreg %reg0) #0 {
6 %r0 = extractelement <4 x float> %reg0, i32 0
Dfloor.ll4 define void @test(<4 x float> inreg %reg0) #0 {
5 %r0 = extractelement <4 x float> %reg0, i32 0
Dcomplex-folding.ll5 define void @main(<4 x float> inreg %reg0) #0 {
7 %0 = extractelement <4 x float> %reg0, i32 0
Dinput-mods.ll12 define void @test(<4 x float> inreg %reg0) #0 {
13 %r0 = extractelement <4 x float> %reg0, i32 0
Dshared-op-cycle.ll7 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 {
8 %w0 = extractelement <4 x float> %reg0, i32 3
Dfmin_legacy.f64.ll6 define void @test_fmin_legacy_f64(<4 x double> addrspace(1)* %out, <4 x double> inreg %reg0) #0 {
7 %r0 = extractelement <4 x double> %reg0, i32 0
8 %r1 = extractelement <4 x double> %reg0, i32 1
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_fragshader.c48 GLuint reg0 = 0; in r200SetFragShaderArg() local
76 reg0 |= (((index - GL_REG_0_ATI)*2) + 10 + useOddSrc) << (5*argPos); in r200SetFragShaderArg()
79 reg0 |= (R200_TXC_ARG_A_TFACTOR_COLOR + useOddSrc) << (5*argPos); in r200SetFragShaderArg()
84 reg0 |= (R200_TXC_ARG_A_TFACTOR1_COLOR + useOddSrc) << (5*argPos); in r200SetFragShaderArg()
89 reg0 |= (R200_TXC_ARG_A_DIFFUSE_COLOR + useOddSrc) << (5*argPos); in r200SetFragShaderArg()
92 reg0 |= (R200_TXC_ARG_A_SPECULAR_COLOR + useOddSrc) << (5*argPos); in r200SetFragShaderArg()
96 reg0 |= R200_TXC_COMP_ARG_A << (4*argPos); in r200SetFragShaderArg()
100 reg0 ^= R200_TXC_COMP_ARG_A << (4*argPos); in r200SetFragShaderArg()
102 reg0 |= R200_TXC_BIAS_ARG_A << (4*argPos); in r200SetFragShaderArg()
104 reg0 |= R200_TXC_SCALE_ARG_A << (4*argPos); in r200SetFragShaderArg()
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/external/v8/test/unittests/interpreter/
Dbytecode-register-allocator-unittest.cc155 int reg0 = allocator()->BorrowTemporaryRegisterNotInRange(0, 3); in TEST_F() local
156 CHECK_EQ(reg0, 4); in TEST_F()
161 allocator()->ReturnTemporaryRegister(reg0); in TEST_F()
200 Register reg0 = allocator.NextConsecutiveRegister(); in TEST_F() local
207 CHECK(Register::AreContiguous(reg0, reg1, reg2, reg3)); in TEST_F()
/external/elfutils/tests/
Drun-varlocs.sh71 [400524,400528) {reg0}
74 [40052e,400531) {reg0}
/external/clang/test/OpenMP/
Dthreadprivate_messages.cpp102 register int reg0 __asm__("esp"); // expected-note {{'reg0' defined here}}
103 #pragma omp threadprivate (reg0) // expected-error {{variable 'reg0' cannot be threadprivate becaus…
Dfor_loop_messages.cpp18 int reg0; variable
320 for (reg0 = 0; reg0 < 10; reg0 += 1) in test_iteration_spaces()
321 c[reg0] = a[reg0]; in test_iteration_spaces()

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