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Searched refs:reg4 (Results 1 – 25 of 43) sorted by relevance

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/external/libvpx/libvpx/vpx_dsp/mips/
Didct32x32_msa.c44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
58 DOTP_CONST_PAIR(reg0, reg4, cospi_16_64, cospi_16_64, reg0, reg4); in idct32x8_row_even_process_store()
60 BUTTERFLY_4(reg4, reg0, reg2, reg6, vec1, vec3, vec2, vec0); in idct32x8_row_even_process_store()
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
67 DOTP_CONST_PAIR(reg4, reg3, cospi_14_64, cospi_18_64, reg4, reg3); in idct32x8_row_even_process_store()
71 vec0 = reg0 + reg4; in idct32x8_row_even_process_store()
72 reg0 = reg0 - reg4; in idct32x8_row_even_process_store()
73 reg4 = reg6 + reg2; in idct32x8_row_even_process_store()
82 reg2 = reg3 + reg4; in idct32x8_row_even_process_store()
[all …]
Didct16x16_msa.c15 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_rows_msa() local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vpx_idct16_1d_rows_msa()
24 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
32 DOTP_CONST_PAIR(reg4, reg12, cospi_24_64, cospi_8_64, reg4, reg12); in vpx_idct16_1d_rows_msa()
33 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vpx_idct16_1d_rows_msa()
34 SUB4(reg2, loc1, reg14, loc0, reg6, loc3, reg10, loc2, reg0, reg12, reg4, in vpx_idct16_1d_rows_msa()
75 loc1 = reg4 + loc0; in vpx_idct16_1d_rows_msa()
76 loc2 = reg4 - loc0; in vpx_idct16_1d_rows_msa()
80 BUTTERFLY_4(reg8, reg10, reg11, reg5, loc0, reg4, reg9, loc1); in vpx_idct16_1d_rows_msa()
[all …]
/external/elfutils/tests/
Drun-varlocs.sh59 [400500,400504) {reg4}
67 [400510,40051c) {reg4}
69 [40052a,400531) {GNU_entry_value(1) {reg4}, stack_value}
82 [400400,400403) {reg4}
83 [400403,40040b) {GNU_entry_value(1) {reg4}, stack_value}
110 [400400,400408) {reg4}
111 [400408,400423) {GNU_entry_value(1) {reg4}, stack_value}
Drun-readelf-zdebug-rel.sh87 [ 0] reg4
Drun-addrcfi.sh37 integer reg4 (%esp): location expression: call_frame_cfa stack_value
84 integer reg4 (%esp): location expression: call_frame_cfa stack_value
136 integer reg4 (%rsi): undefined
202 integer reg4 (%rsi): undefined
306 integer reg4 (r4): undefined
1328 integer reg4 (r4): undefined
2356 integer reg4 (r4): undefined
3382 integer reg4 (%r4): undefined
3459 integer reg4 (%r4): undefined
3537 integer reg4 (r4): same_value
[all …]
/external/llvm/test/CodeGen/ARM/
Dfast-isel-pic.ll45 ; THUMB-ELF: ldr r[[reg4:[0-9]+]], [r[[reg3]]]
46 ; THUMB-ELF: ldr r0, [r[[reg4]]]
48 ; ARM: ldr [[reg4:r[0-9]+]],
49 ; ARM: ldr [[reg4]], [pc, [[reg4]]]
/external/libxml2/result/HTML/
Dreg4.html.err1 ./test/HTML/reg4.html:10: HTML parser error : Unexpected end tag : p
/external/llvm/test/CodeGen/AMDGPU/
Dpv.ll6 …eg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg …
20 %12 = extractelement <4 x float> %reg4, i32 0
21 %13 = extractelement <4 x float> %reg4, i32 1
22 %14 = extractelement <4 x float> %reg4, i32 2
23 %15 = extractelement <4 x float> %reg4, i32 3
Dbig_alu.ll6 …eg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg …
38 %30 = extractelement <4 x float> %reg4, i32 0
39 %31 = extractelement <4 x float> %reg4, i32 1
40 %32 = extractelement <4 x float> %reg4, i32 2
41 %33 = extractelement <4 x float> %reg4, i32 3
/external/llvm/test/DebugInfo/
Ddwarfdump-debug-frame-simple.test9 ; FRAMES: DW_CFA_def_cfa: reg4 +4
/external/llvm/test/MC/X86/
Di386-darwin-frame-register.ll14 ; CHECK: DW_CFA_def_cfa: reg4 +4
/external/v8/src/interpreter/
Dbytecodes.cc908 Register reg4, Register reg5) { in AreContiguous() argument
915 if (reg4.is_valid() && reg3.index() + 1 != reg4.index()) { in AreContiguous()
918 if (reg5.is_valid() && reg4.index() + 1 != reg5.index()) { in AreContiguous()
Dbytecodes.h403 Register reg4 = Register(),
/external/vixl/src/vixl/a64/
Dmacro-assembler-a64.cc2456 const Register& reg4) { in Include() argument
2458 RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); in Include()
2469 const FPRegister& reg4) { in Include() argument
2470 RegList include = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); in Include()
2488 const Register& reg4) { in Exclude() argument
2489 RegList exclude = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); in Exclude()
2497 const FPRegister& reg4) { in Exclude() argument
2498 RegList excludefp = reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit(); in Exclude()
2506 const CPURegister& reg4) { in Exclude() argument
2510 const CPURegister regs[] = {reg1, reg2, reg3, reg4}; in Exclude()
Dassembler-a64.h413 const CPURegister& reg4 = NoReg,
427 const CPURegister& reg4 = NoCPUReg,
440 const VRegister& reg4 = NoVReg);
450 const VRegister& reg4 = NoVReg);
459 CPURegister reg4 = NoCPUReg)
460 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
462 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4));
Dassembler-a64.cc5401 const CPURegister& reg3, const CPURegister& reg4, in AreAliased() argument
5410 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
5436 const CPURegister& reg3, const CPURegister& reg4, in AreSameSizeAndType() argument
5443 match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1); in AreSameSizeAndType()
5453 const VRegister& reg3, const VRegister& reg4) { in AreSameFormat() argument
5458 match &= !reg4.IsValid() || reg4.IsSameFormat(reg1); in AreSameFormat()
5464 const VRegister& reg3, const VRegister& reg4) { in AreConsecutive() argument
5471 match &= !reg4.IsValid() || in AreConsecutive()
5472 (reg4.code() == ((reg1.code() + 3) % kNumberOfVRegisters)); in AreConsecutive()
Dmacro-assembler-a64.h3287 const Register& reg4 = NoReg);
3291 const VRegister& reg4 = NoVReg);
3301 const Register& reg4 = NoReg);
3305 const VRegister& reg4 = NoVReg);
3309 const CPURegister& reg4 = NoCPUReg);
/external/v8/src/arm64/
Dassembler-arm64.h345 Register reg4 = NoReg);
353 const CPURegister& reg4 = NoReg,
366 const CPURegister& reg4 = NoCPUReg,
385 CPURegister reg4 = NoCPUReg)
386 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
388 DCHECK(AreSameSizeAndType(reg1, reg2, reg3, reg4));
Dassembler-arm64.cc208 Register reg3, Register reg4) { in GetAllocatableRegisterThatIsNotOneOf() argument
209 CPURegList regs(reg1, reg2, reg3, reg4); in GetAllocatableRegisterThatIsNotOneOf()
223 const CPURegister& reg3, const CPURegister& reg4, in AreAliased() argument
232 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
260 const CPURegister& reg3, const CPURegister& reg4, in AreSameSizeAndType() argument
267 match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1); in AreSameSizeAndType()
/external/v8/src/arm/
Dmacro-assembler-arm.cc3882 Register reg4, in GetRegisterThatIsNotOneOf() argument
3889 if (reg4.is_valid()) regs |= reg4.bit(); in GetRegisterThatIsNotOneOf()
3947 Register reg4, in AreAliased() argument
3953 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
3960 if (reg4.is_valid()) regs |= reg4.bit(); in AreAliased()
Dmacro-assembler-arm.h67 Register reg4 = no_reg,
76 Register reg4 = no_reg,
/external/llvm/include/llvm/Support/
DDwarf.def200 HANDLE_DW_OP(0x54, reg4)
/external/libvpx/libvpx/vpx_dsp/arm/
Didct32x32_add_neon.asm241 …BUTTERFLY $regC, $regD, $regA, $regB, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
279 vqrshrn.s32 $reg4, q10, #14
286 DO_BUTTERFLY_STD $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
287 DO_BUTTERFLY d28, d29, d26, d27, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
/external/v8/src/ppc/
Dmacro-assembler-ppc.cc4734 Register reg4, Register reg5, in GetRegisterThatIsNotOneOf() argument
4740 if (reg4.is_valid()) regs |= reg4.bit(); in GetRegisterThatIsNotOneOf()
4794 bool AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, in AreAliased() argument
4798 reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
4806 if (reg4.is_valid()) regs |= reg4.bit(); in AreAliased()
/external/v8/src/s390/
Dmacro-assembler-s390.cc3689 Register reg4, Register reg5, in GetRegisterThatIsNotOneOf() argument
3695 if (reg4.is_valid()) regs |= reg4.bit(); in GetRegisterThatIsNotOneOf()
5438 bool AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, in AreAliased() argument
5442 reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
5450 if (reg4.is_valid()) regs |= reg4.bit(); in AreAliased()

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